Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

468

Datasheet

GPIO Control Registers GPIO I2C register (gmbus_register.v reg_gpio0, reg_gpio1, 

reg_gpio2. reg_gpio3, reg_gpio4)

Default: 00000808h

3

1b

RW

This is the value that should be place on the 

GPIO Clk pin as an output. This value is only written into the register if GPIO Clock DATA 

MASK is also asserted. The value will appear on the pin if this data value is actually 

written to this register and the GPIO Clock DIRECTION VALUE contains a value that will 

configure the pin as an output. 

Default = 1. The GPIO default clock data value is programmed to 1 in hardware. The 

hardware drives a default of 1 since the I2C interface defaults to a 1 . (this mimics the 

I2C external pull-ups on the bus)

2

0b

WO

This is a mask bit to determine whether the GPIO 

Clock DATA VALUE bit should be written into the register. This value is not stored and 

when read always returns 0. 

0 = Do NOT write GPIO Clock Data Value bit (default). 

1 = Write GPIO Clock Data Value bit.  

AccessType: Write Only

1

0b

RW

This is the value that should be used to 

define the output enable of the GPIO Clock pin. This value is only written into the 

register if GPIO Clock DIRECTION MASK is also asserted. The value that will appear on 

the pin is defined by what is in the register for the GPIO Clock DATA VALUE bit.  

0 = Pin is configured as an input and the output driver is set to tri-state (default) 

1 = Pin is configured as an output.

0

0b

WO

This is a mask bit to determine whether the 

GPIO Clock DIRECTION VALUE bit should be written into the register. This value is not 

stored and when read returns 0. 

0 = Do NOT update the GPIO Clock Direction Value bit on a write (default). 

1 = Update the GPIO Clock Direction Value bit. on a write operation to this register.  

AccessType: Write Only

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0

RE

SER

V

ED

GP

IO_DA

TA_IN_RO

GP

IO_DA

TA_

V

A

LU

E_R_W

GP

IO_DA

TA_MA

SK_WO

GPIO_DA

TA_DIRECTION_

V

A

LU

E_R_W

GP

IO_DA

TA_

DIRECTION_MASK_WO

RE

S

E

R

V

E

D

_

1

G

PIO_CL

O

C

K

_DA

TA_IN_RO

G

P

IO

_

C

LOCK

_

D

A

TA_

V

A

LU

E_

R

_

W

GPIO_CL

O

CK_DA

TA_MASK_WO

GP

IO_C

LO

CK_DIRECTION_

V

AL

U

E

_R_W

G

PIO_CL

O

C

K

_

D

IRECTION_MASK_WO