Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

504

Datasheet

GMBUS frequency binary encoding GMBUS Frequency Binary Encoding Register.

Default: 000000A0h

24

0b

RW

0 = Enable clock gating for AES clock (default) 

1 = Disable clock gating for AES clock

23:15

0b

RW

Reserved.

14

1b

RW

0 = Fast Mode enabled. The Gfx mem arbiter can 

accept a vga display read request every clock. Note that the HP Address 

(G_HP_CONTROL[28:24]) and ID (G_HP_CONTROL[21:16]) FIFO depths must be set to 

a value greater than 1 when Fast Mode is enabled. 

1 = Fast Mode disabled. (default) The Gfx mem arbiter can accept a vga display read 

request every other clock 

Programming note: VGA FAST MODE is not supported in VLVP.

13:4

0b

RW

If bit 3 of this register is set, the 10-btt Request 

Latency Override value programmed here is used as the latency offset from the global 

timer for requests that win arbitration. If bit 3 is not set, normal request latency from 

streamers is used.  

Programming note: This value should not be larger than the actual required request 

latency. Otherwise, it will cause underrun. The guidline is to use latency corresponds to 

low watermark level or even smaller. When this field is used, the actual request latency 

is defeatured, either zero or a small value is used but still not causing underrun.

3

0b

RW

1 = Request Latency Override values in 

bit[13:4] is used as the latency offset from global timer 

0 = Request Latency Override values is disabled. Normal request latency from streamer 

is used. (default)

2

0b

RW

0 = AES decryption engine is enabled 

(Default) 

1 = AES decryption engine is bypassed

1

0b

RW

0 = Disable sending AES 

session keys to AES when going from Panel Self Refresh (PSR) inactive to PSR active 

mode (Default). Hardware is responsible to clear this bit after this bit is set to resend 

the session keys. 

1 = Enable sending AES session keys to AES engine when going from PSR inactive to 

PSR active mode. When driver sets this bit, PAVP engine will resend the session keys to 

AES engine. Hardware is responsible to clear this bit after the session keys are sent.

0

0b

RW

0 = Select hierarchical arbiter 

1 = Select backup round robin arbiter

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h