Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

588

Datasheet

Default: 00000000h

Pipe A Horizontal Blank Register

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RE

SE

RVED

PIP

E

_A_HO

R

IZ

ONT

A

L_T

O

TA

L_D

ISPLA

Y_CL

OCKS

RESE

RVE

D

_1

PIPE

_A

_HO

R

IZONT

A

L_A

C

TI

VE_DISPLA

Y

_E

ND_PI

X

ELS

31:29

0b

RW

Write as zero.

28:16

0b

RW

This 13-bit field provides 

Horizontal Total up to 8192 pixels encompassing the Horizontal Active Display period, 

front/back border and retrace period. Any pending event (HSYNC, ACTIVE, HBLANK) is 

reset at HTOTAL and the programmed sequence begins again. This field is programmed 

to the number of clocks desired minus one.  

This number of clocks needs to be a multiple of two when driving data out the digital 

port out the LVDS port in two channel mode. This value should always be equal or 

greater to the sum of the horizontal active and the horizontal blank, and border region 

sizes.

15:12

0b

RW

Write as zero.

11:0

0b

RW

This 12-bit field provides 

Horizontal Active Display resolutions up to 4096 pixels. Note that the first horizontal 

active display pixel is considered pixel number 0. The value programmed should be the 

(active pixels/line 1).  

The number of active pixels will be limited to multiples of two pixels when driving the 

integrated LVDS port in two channel mode. For proper results during VGA centering 

mode this value needs to be large enough to fit the largest VGA mode supported, this 

should be at least 720/1440 pixels for standard VGA type modes or 640/1280 pixels if 

the nine-dot disable bit in the VGA control register is set. When using the internal panel 

fitting logic, the minimum horizontal size allowed will be three pixels.