Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
589
Access Method
Default: 00000000h
14.10.152 HSYNC_A—Offset 60008h
Pipe A Horizontal Sync Register
Access Method
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RE
SERV
ED
PIPE
_A
_HO
R
IZONT
A
L_BLANK_E
N
D
RE
SERV
ED_1
PIPE
_A
_HO
R
IZONT
A
L_
B
LANK
_
S
TAR
T
Bit
Range
Default &
Access
Field Name (ID): Description
31:29
0b
RW
RESERVED:
Read Only.
28:16
0b
RW
PIPE_A_HORIZONTAL_BLANK_END:
This 13-bit field specifies the position of
Horizontal Blank End expressed in terms of the absolute pixel number relative to the
horizontal active display start. The value programmed should be the HBLANK End pixel
position, where the first active pixel is considered position 0; the second active pixel is
considered position 1, etc. Horizontal blank ending at the same point as the horizontal
total indicates that there is no left hand border area. HBLANK size has a minimum value
of 32 clocks.
The number of clocks within blank needs to be a multiple of two when driving data out
LVDS in two channel mode.
The value loaded in the register would be equal to RightBorder+Active+HBlank-1.
If this pipe is connected to the TVout port or Panel Fitter 2 the border must be zero. In
that case this register is programmed to the same value as the HTOTAL register.
15:13
0b
RW
RESERVED_1:
Read Only.
12:0
0b
RW
PIPE_A_HORIZONTAL_BLANK_START:
This 13-bit field specifies the Horizontal
Blank Start position expressed in terms of the absolute pixel number relative to the
horizontal active display start. The value programmed should be the HBLANK Start pixel
position, where the first active pixel is considered position 0; the second active pixel is
considered position 1, etc.
The number of clocks for both left and right borders need to be a multiple of two when
driving data out the LVDS port in two channel mode. Horizontal blank should only start
after the end of the horizontal active region.
The value loaded in the register would be equal to RightBorder+Active-1.
If this pipe is connected to the TVout port or Panel Fitter 2 the border must be zero. In
that case this register is programmed to the same value as the HACTIVE register.