Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
593
14.10.156 PIPESRCA—Offset 6001Ch
Pipe A Source Image Size
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RE
SE
RVED
PIPE
_A_
V
E
R
TIC
A
L_S
Y
N
C
_E
ND
RESE
RVED
_1
PIPE
_A_
V
E
R
TIC
A
L_S
Y
N
C
_S
TA
R
T
Bit
Range
Default &
Access
Field Name (ID): Description
31:29
0b
RW
RESERVED:
Read Only.
28:16
0b
RW
PIPE_A_VERTICAL_SYNC_END:
This 13-bit field specifies the Vertical Sync End
position expressed in terms of the absolute Line number relative to the vertical active
display start. The value programmed should be the VSYNC End line position, where the
first active line is considered line 0, the second active line is considered line 1, etc. This
register should be loaded with Vactive+BottomBorder+FrontPorch+Sync-1. For
interlaced display modes, hardware automatically divides this number by 2 to get the
vertical sync end in each field. It does not count the two half lines that get added when
operating in modes with half lines.
15:13
0b
RW
RESERVED_1:
Read Only.
12:0
0b
RW
PIPE_A_VERTICAL_SYNC_START:
This 13-bit field specifies the Vertical Sync Start
position expressed in terms of the absolute line number relative to the vertical active
display start. The value programmed should be the VSYNC Start line position, where the
first active line is considered line 0, the second active line is considered line 1, etc. This
register would be loaded with Vactive+BottomBorder+FrontPorch-1. For interlaced
display modes, hardware automatically divides this number by 2 to get the vertical sync
start in each field. It does not count the two half lines that get added when operating in
modes with half lines.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h