Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

620

Datasheet

Video Data Island Packet Data for Pipe A 

Default: 00000000h

Video Data Island Payload for Pipe A 

11:8

1001b

RO

Project: All  

AccessType: Read Only  

Default Value: ;1001b  

This reflects the buffer size in dwords available for the type of Video DIP being indexed 

by bits 20:19 of this register, including the header. It is hardwired to the maximum size 

of a Video DIP, 36 bytes. Please note that this count includes ECC bytes, which are not 

writable by software. These bits are immediately valid after write of the DIP index. 

7:4

0b

RW

Project: All Format: MBZ 

3:0

0b

RO

Project: All  

AccessType: Read Only  

Selects the DWORD address for access to the Video DIP buffers. This value is 

automatically incremented after each read or write of the Video DIP Data Register. The 

value wraps back to zero when it autoincrements past the max address value of 0xF. 

This field change takes effect immediately after being written. The read value indicates 

the current access address. 

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VIDE

O_DIP_DA

TA

31:0

0b

RW

Project: All  

When read, this returns the current value at the location specified in the Video DIP 

buffer index select and Video DIP RAM access address fields. The index used to address 

the RAM is incremented after each read or write of this register. DIP data can be read at 

any time. Data should be loaded into the RAM before enabling the transmission through 

the DIP type enable bit. Accesses to this register are on a per-DWORD basis.