Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

636

Datasheet

61178–6117Bh

4

“VIDEO_DIP_GDCP_PAYLOAD_B—Offset 61178h” on page 685

00000000h

61190–61193h

4

“MIPIA_PORT_CTRL—Offset 61190h” on page 686

00000000h

61194–61197h

4

“MIPIA_TEARING_CTR—Offset 61194h” on page 689

00000000h

61198–6119Bh

4

“DPA_PIX_GEN_CTRL—Offset 61198h” on page 689

00000000h

611A0–611A3h

4

“MIPIA_AUTOPWG—Offset 611A0h” on page 691

00000000h

611B0–611B3h

4

“DPB_PIX_GEN_CTRL—Offset 611B0h” on page 691

00000000h

61200–61203h

4

“PIPEA_PP_STATUS—Offset 61200h” on page 693

08000000h

61204–61207h

4

“PIPEA_PP_CONTROL—Offset 61204h” on page 694

00000000h

61208–6120Bh

4

“PIPEA_PP_ON_DELAYS—Offset 61208h” on page 696

00000000h

6120C–6120Fh

4

“PIPEA_PP_OFF_DELAYS—Offset 6120Ch” on page 697

00000000h

61210–61213h

4

“PIPEA_PP_DIVISOR—Offset 61210h” on page 698

00270F04h

61230–61233h

4

“PFIT_CONTROL—Offset 61230h” on page 699

20000000h

61234–61237h

4

“PFIT_PGM_RATIOS—Offset 61234h” on page 701

00000000h

61238–6123Bh

4

“RESERVEDUSEDTOBEAUTOSCALINGRATIOSREADBACK—Offset 61238h” on

00000000h

6123C–6123Fh

4

“RESERVEDUSEDTOBESCALINGINITIALPHASE—Offset 6123Ch” on page 702

00000000h

61250–61253h

4

“PIPEA_BLC_PWM_CLT2—Offset 61250h” on page 703

00000000h

61254–61257h

4

“PIPEA_BLC_PWM_CTL—Offset 61254h” on page 704

00000000h

61260–61263h

4

“PIPEA_BLM_HIST_CTL—Offset 61260h” on page 705

00000000h

61264–61267h

4

“PIPEA_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER—Offset 61264h” on

00000000h

61268–6126Bh

4

“PIPEAHISTOGRAMTHRESHOLDGUARDBANDREGISTER—Offset 61268h” on

00000000h

61300–61303h

4

“PIPEB_PP_STATUS—Offset 61300h” on page 708

08000000h

61304–61307h

4

“PIPEB_PP_CONTROL—Offset 61304h” on page 710

00000000h

61308–6130Bh

4

“PIPEB_PP_ON_DELAYS—Offset 61308h” on page 712

00000000h

6130C–6130Fh

4

“PIPEB_PP_OFF_DELAYS—Offset 6130Ch” on page 713

00000000h

61310–61313h

4

“PIPEB_PP_DIVISOR—Offset 61310h” on page 713

00270F04h

61350–61353h

4

“PIPEB_BLC_PWM_CLT2—Offset 61350h” on page 714

00000000h

61354–61357h

4

“PIPEB_BLC_PWM_CTL—Offset 61354h” on page 716

00000000h

61360–61363h

4

“PIPEB_BLM_HIST_CTL—Offset 61360h” on page 716

00000000h

61364–61367h

4

“PIPEB_IMAGE_ENHANCEMENT_BIN_DATA_REGISTER—Offset 61364h” on

00000000h

61368–6136Bh

4

“PIPEBHISTOGRAMTHRESHOLDGUARDBANDREGISTER—Offset 61368h” on

00000000h

61700–61703h

4

“MIPIC_PORT_CTRL—Offset 61700h” on page 720

00000000h

61704–61707h

4

“MIPIC_TEARING_CTR—Offset 61704h” on page 721

00000000h

62000–62003h

4

“AUD_CONFIG_A—Offset 62000h” on page 722

00000000h

62010–62013h

4

“AUD_MISC_CTRL_A—Offset 62010h” on page 723

00000044h

62020–62023h

4

“AUD_VID_DID—Offset 62020h” on page 724

80862882h

62024–62027h

4

“AUD_RID—Offset 62024h” on page 725

00100000h

Table 171.

Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default

Value