Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

Datasheet

639

6505C–6505Fh

4

“STREAM_A_LPE_AUD_BUF_D_LENGTH—Offset 6505Ch” on page 807

00000000h

65060–65063h

4

“STREAM_A_LPE_AUD_CNTL_ST—Offset 65060h” on page 807

00000000h

65064–65067h

4

“STREAM_A_LPE_AUD_HDMI_STATUS—Offset 65064h” on page 809

00000000h

65068–6506Bh

4

“STREAM_A_LPE_AUD_HDMIW_INFOFR—Offset 65068h” on page 811

00000000h

65800–65803h

4

“STREAM_B_LPE_AUD_CONFIG—Offset 65800h” on page 811

00000280h

65808–6580Bh

4

“STREAM_B_LPE_AUD_CH_STATUS_0—Offset 65808h” on page 813

00000000h

6580C–6580Fh

4

“STREAM_B_LPE_AUD_CH_STATUS_1—Offset 6580Ch” on page 814

00000000h

65810–65813h

4

“STREAM_B_LPE_AUD_HDMI_CTS_DP_MAUD—Offset 65810h” on page 815

00000000h

65814–65817h

4

“STREAM_B_LPE_AUD_HDMI_N_DP_NAUD—Offset 65814h” on page 815

00000000h

65820–65823h

4

“STREAM_B_LPE_AUD_BUFFER_CONFIG—Offset 65820h” on page 816

00000100h

65824–65827h

4

“STREAM_B_LPE_AUD_BUF_CH_SWP—Offset 65824h” on page 817

00FAC688h

65840–65843h

4

“STREAM_B_LPE_AUD_BUF_A_ADDR—Offset 65840h” on page 819

00000000h

65844–65847h

4

“STREAM_B_LPE_AUD_BUF_A_LENGTH—Offset 65844h” on page 819

00000000h

65848–6584Bh

4

“STREAM_B_LPE_AUD_BUF_B_ADDR—Offset 65848h” on page 820

00000000h

6584C–6584Fh

4

“STREAM_B_LPE_AUD_BUF_B_LENGTH—Offset 6584Ch” on page 821

00000000h

65850–65853h

4

“STREAM_B_LPE_AUD_BUF_C_ADDR—Offset 65850h” on page 821

00000000h

65854–65857h

4

“STREAM_B_LPE_AUD_BUF_C_LENGTH—Offset 65854h” on page 822

00000000h

65858–6585Bh

4

“STREAM_B_LPE_AUD_BUF_D_ADDR—Offset 65858h” on page 822

00000000h

6585C–6585Fh

4

“STREAM_B_LPE_AUD_BUF_D_LENGTH—Offset 6585Ch” on page 823

00000000h

65860–65863h

4

“STREAM_B_LPE_AUD_CNTL_ST—Offset 65860h” on page 824

00000000h

65864–65867h

4

“STREAM_B_LPE_AUD_HDMI_STATUS—Offset 65864h” on page 825

00000000h

65868–6586Bh

4

“STREAM_B_LPE_AUD_HDMIW_INFOFR—Offset 65868h” on page 827

00000000h

70000–70003h

4

“PIPEA_DSL—Offset 70000h” on page 828

00000000h

70004–70007h

4

“PIPEA_SLC—Offset 70004h” on page 828

00000000h

70008–7000Bh

4

“PIPEACONF—Offset 70008h” on page 829

00000000h

70010–70013h

4

“PIPEAGCMAXRED—Offset 70010h” on page 836

00010000h

70014–70017h

4

“PIPEAGCMAXGREEN—Offset 70014h” on page 837

00010000h

70018–7001Bh

4

“PIPEAGCMAXBLUE—Offset 70018h” on page 838

00010000h

70024–70027h

4

“PIPEASTAT—Offset 70024h” on page 839

00000000h

70028–7002Bh

4

“DPFLIPSTAT—Offset 70028h” on page 843

00000000h

7002C–7002Fh

4

“DPINVGTT—Offset 7002Ch” on page 845

00000000h

70030–70033h

4

“DSPARB—Offset 70030h” on page 847

80008000h

70034–70037h

4

“FW1—Offset 70034h” on page 848

3F8F0F0Fh

70038–7003Bh

4

“FW2—Offset 70038h” on page 849

0B0F0F0Fh

7003C–7003Fh

4

“FW3—Offset 7003Ch” on page 851

00000000h

70040–70043h

4

“PIPEAFRAMECOUNT—Offset 70040h” on page 852

00000000h

70044–70047h

4

“PIPEAFLIPCOUNT—Offset 70044h” on page 852

00000000h

70048–7004Bh

4

“PIPEAMSAMISC—Offset 70048h” on page 853

00000000h

70050–70053h

4

“DDL1—Offset 70050h” on page 854

00000000h

Table 171.

Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default

Value