Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

642

Datasheet

7141C–7141Fh

4

“SWF13—Offset 7141Ch” on page 938

00000000h

71420–71423h

4

“SWF14—Offset 71420h” on page 938

00000000h

71424–71427h

4

“SWF15—Offset 71424h” on page 939

00000000h

71428–7142Bh

4

“SWF16—Offset 71428h” on page 939

00000000h

7142C–7142Fh

4

“SWF17—Offset 7142Ch” on page 940

00000000h

71430–71433h

4

“SWF18—Offset 71430h” on page 940

00000000h

71434–71437h

4

“SWF19—Offset 71434h” on page 941

00000000h

71438–7143Bh

4

“SWF1A—Offset 71438h” on page 941

00000000h

7143C–7143Fh

4

“SWF1B—Offset 7143Ch” on page 942

00000000h

71440–71443h

4

“SWF1C—Offset 71440h” on page 942

00000000h

71444–71447h

4

“SWF1D—Offset 71444h” on page 943

00000000h

71448–7144Bh

4

“SWF1E—Offset 71448h” on page 943

00000000h

7144C–7144Fh

4

“SWF1F—Offset 7144Ch” on page 944

00000000h

72180–72183h

4

“SPACNTR—Offset 72180h” on page 944

00000000h

72184–72187h

4

“SPALINOFF—Offset 72184h” on page 947

00000000h

72188–7218Bh

4

“SPASTRIDE—Offset 72188h” on page 948

00000000h

7218C–7218Fh

4

“SPAPOS—Offset 7218Ch” on page 948

00000000h

72190–72193h

4

“SPASIZE—Offset 72190h” on page 949

00000000h

72194–72197h

4

“SPAKEYMINVAL—Offset 72194h” on page 950

00000000h

72198–7219Bh

4

“SPAKEYMSK—Offset 72198h” on page 950

00000000h

7219C–7219Fh

4

“SPASURF—Offset 7219Ch” on page 951

00000000h

721A0–721A3h

4

“SPAKEYMAXVAL—Offset 721A0h” on page 953

00000000h

721A4–721A7h

4

“SPATILEOFF—Offset 721A4h” on page 954

00000000h

721A8–721ABh

4

“SPACONTALPHA—Offset 721A8h” on page 954

00000000h

721AC–721AFh

4

“SPALIVESURF—Offset 721ACh” on page 955

00000000h

721D0–721D3h

4

“SPACLRC0—Offset 721D0h” on page 957

01000000h

721D4–721D7h

4

“SPACLRC1—Offset 721D4h” on page 958

00000080h

721E0–721E3h

4

“SPAGAMC5—Offset 721E0h” on page 959

00C0C0C0h

721E4–721E7h

4

“SPAGAMC4—Offset 721E4h” on page 960

00808080h

721E8–721EBh

4

“SPAGAMC3—Offset 721E8h” on page 960

00404040h

721EC–721EFh

4

“SPAGAMC2—Offset 721ECh” on page 961

00202020h

721F0–721F3h

4

“SPAGAMC1—Offset 721F0h” on page 961

00101010h

721F4–721F7h

4

“SPAGAMC0—Offset 721F4h” on page 962

00080808h

72280–72283h

4

“SPBCNTR—Offset 72280h” on page 963

00000000h

72284–72287h

4

“SPBLINOFF—Offset 72284h” on page 965

00000000h

72288–7228Bh

4

“SPBSTRIDE—Offset 72288h” on page 966

00000000h

7228C–7228Fh

4

“SPBPOS—Offset 7228Ch” on page 967

00000000h

72290–72293h

4

“SPBSIZE—Offset 72290h” on page 967

00000000h

72294–72297h

4

“SPBKEYMINVAL—Offset 72294h” on page 968

00000000h

Table 171.

Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default

Value