Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

679

display digital poty hot plug control register

9

0b

RW

This bit enables a null packet (32 

bytes of a value of 0) to be sent when Vsync=1 on this port, required for HDMI 

operation. It also enables preambles and guardbands prior to the null packets, in 

accordance with the HDMI specification. It is only valid for modes that use TMDS 

encoding.  

0 = Disable null infoframe packets when Vsync=1 on this port. (Default) 

1 = Enable null infoframe packets when Vsync=1 on this port.

8

0b

RW

This bit is used to select the color range of RBG outputs in 

HDMI mode. It is only valid when using TMDS encoding and 8 bit per color mode. 

0 = Apply full 0-255 color range to the output (Default) 

1 = Apply 16-235 color range to the output ([DevCL and DevCTG] only)

7

0b

RW

This bit determines if the border data from native VGA or 

the timing generator is to be considered valid pixel data at the external component. 

1 = Border to the sDVOC encoder is enabled. Blank# is used to generate the DE output 

(used in all cases except when the external scaler is used in a DVI panel, over SDVO) . 

0 = Border to the sDVOC encoder is disabled. DE (Display Enable) is used

6

0b

RW

([DevCL, DevCTG, DevCDV]): This bit directs audio to this 

port. When enabled and audio data is available, the audio data will be combined with 

the video data and sent over this port. The audio unit uses the status of this bit to 

indicate presence of the HDMI output to the audio driver.  

0 = (Default) No audio output on this port 

1 = Enable audio on this port ([DevCL, DevCTG, DevCDV] only)

5

0b

RW

This bit directs HDCP to this port. When enabled, the 

information sent on this port will be encrypted using HDCP. Please note that this bit does 

not enable encryption on its own, but must be used in conjunction with HDCP registers. 

0 = (Default) No HDCP encryption on this port 

1 = Enable HDCP on this port ([DevCL, DevCTG, DevCDV] only)

4:3

11b

RW

Please note that sync polarity does not apply to ANSI coding. 

Indicates the polarity of Hsync and Vsync. Inverted polarity is transmitted as SYNC-

BLANK-SYNC and standard polarity is transmitted as BLANK-SYNC-BLANK. For example, 

if Vsync is not inverted and Hsync is inverted, an Hsync period transmitted during Vsync 

would be transmitted as BLANK+VS+HS BLANK+VS BLANK+VS+HS.  

Please note that in native VGA modes, these bits have no effect. In native VGA modes, 

sync polarity is determined by VRshr3c2d76b[7:6], the VGA polarity bits in VGA control. 

00 = VS and HS are active low (inverted) 

01 = VS is active low (inverted), HS is active high 

10 = VS is active high, HS is active low (inverted) 

11 = (Default) VS and HS are active high

2

0b

RO

Read-only bit indicating whether a digital port C was 

detected during initialization. It signifies the level of the GMBUS port 3 (port C) data line 

at boot. This bit is valid regardless of whether the port is enabled. 

0 = Digital Port C not detected during initialization 

1 = Digital Port C detected during initialization (default) 

AccessType: Read Only

1

0b

RO

Read-only bit indicating whether the DDI2 port was detected 

during initialization. It signifies the level of the GMBUS port 1 data line at boot. This bit 

is valid regardless of whether the port is enabled. 

0 = DDI2 Port not detected during initialization 

1 = DDI2 Port detected during initialization (default) 

AccessType: Read Only

0

0b

RW

MBZ