Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

709

31

28

24

20

16

12

8

4

0

0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA

N

E

L_

PO

W

E

R

_

O

N

_

S

TA

T

U

S

RE

QU

IRE_A

S

SET

_

ST

A

T

U

S

POWER_S

E

QUENCE_PROGRE

S

S

PO

W

E

R

_

CY

CLE

_

DELA

Y

_

AC

TI

VE

RE

SE

RVED

INTERNA

L_SEQ

UE

NCE

_

ST

A

T

E_FOR_TE

ST_D

EBUG

31

0b

RO

0 = Indicates that the panel power down sequencing 

has completed. A power cycle delay may be currently active. It is safe and allowed to 

program pipe timing and DPLL registers. If this bit is not a zero, it activates the register 

write protect and writes to those registers will be ignored unless the write protect key 

value is set in the panel sequencing control register. 

1 = In conjunction with bits Power Sequence Progress field and Power Cycle Delay 

Active, this bit set to a one indicates that the panel is currently powered up or is 

currently in the power down sequence and it is unsafe to change the pipe timing and 

DPLL registers for the pipe that is assigned to the embedded panel output.  

If the embedded panel port is selected as the target for the panel control, Software is 

responsible for enabling the LCD display by writing a 1 to the port enable bit only after 

all pipe timing, DPLL registers are properly programmed, and the PLL has locked to the 

reference signal. 

This bit is cleared (set to 0) only after the panel power down sequencing is completed.

30

0b

RO

This bit indicates the status of programming of the display 

PLL and the selected display port. This a power on cycle will not be allowed unless this 

status indicates that the required assets are programmed and ready for use. 

0 = All required assets are not properly programmed. 

1 = All required assets are ready for the driving of a panel. 

The following conditions determine that the assets are ready: 

1) Display Pipe PLL Enabled and frequency locked (bit-31 of DPLL Control Register for 

the pipe attached to the embedded panel port). 

2) Display Pipe Enabled (bit-31 of PIPECONF Pipe Configuration Register. For the pipe 

attached to the embedded panel port) 

3) Embedded Panel Port is Programmed Enabled

29:28

0b

RO

00 = Indicates that the panel is not in a power 

sequence 

01 = Indicates that the panel is in a power up sequence (may include power cycle delay) 

10 = Indicates that the panel is in a power down sequence 

11 = Reserved

27

1b

RO

Power cycle delays occur after a panel power down 

sequence or after a hardware reset. On reset, a power cycle delay will occur using the 

default value for the timing. 

0 = A power cycle delay is not currently active 

1 = A power cycle delay (T4) is currently active

26:4

0b

RO

Reserved.