Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

786

Datasheet

28

0b

RW

Project: All  

Default Value: 0b  

Enables test for the DPB-AUX core logic transmit and receive functions through the DPB-

AUX and DPC-AUX buffers. DPB-AUX and DPC-AUX are interconnected through I/O 

buffer loopbacks. DPB-AUX is programmed as source to output a 20 byte test pattern. 

DPC-AUX is programmed as sink to receive the test pattern and reply with a different 20 

byte test pattern. Test pattern 1 = 0xA55CC33E E770080C 0E0F0F8F CFEFF81C 

3E77E3C8 Test pattern 2 = 0X183C7EE7 C381FF7F 3F1F0F07 030100EE 77CC33A5 

Programming sequence: 1. Set DPB-AUX Full Test Enable to 1. 2. Program 

DPB_AUX_CH_DATA[1-5] with test pattern 1 to transmit as the source. 3. Program 

DPC_AUX_CH_DATA[1-5] with test pattern 2 to reply with as the sink. 4. Program all 

DPC_AUX_CH_CTL fields and set Send to 1. 5. Program all DPB_AUX_CH_CTL fields and 

set Send to 1. Then the test will start. Results checking sequence: 1. Poll 

DPB_AUX_CH_CTL for Done. To pass, Done must be set within 500us. 2. Read 

DPB_AUX_CH_CTL register. To pass, Timeout Error and Receive Error must be 0. 3. 

Read DPC_AUX_CH_CTL register. To pass, Receive Error must be 0. 4. Read 

DPB_AUX_CH_DATA[1-5] registers. To pass, they must contain test pattern 2. 5. Read 

DPC_AUX_CH_DATA[1-5] registers. To pass, they must contain test pattern 1. Clear this 

bit to 0 after test is done to return DP-AUX to normal operation. Test must be repeated 

with and without lane reversal to verify DPB-AUX buffer combinations. Only enable one 

DP-AUX Full Test at a time. To abort a test in progress, write the AUX_CH_CTL Send bits 

to 0 and Full Test Enable to 0.  

Value Name Description Project  

0b Disable Test disabled All  

1b Enable Enable test All 

27:16

0b

RW

Project: All Format: 

15

0b

RW

Project: All  

Output just 16 manchester 0s for sync (otherwise 26) 

14

0b

RW

Project: All  

Output neverending Manchester encoded 0s for electrical testing 

13

0b

RW

Project: All  

Tighten the window of allowable receive frequencies 

12

0b

RW

Project: All  

Check for only 8 good sync 0s instead of 12 when receiving 

11:10

0b

RW

Project: All  

Default Value: 0b  

Select clock count for deglitch  

Value Name Description Project  

00b 50 ns 25 clocks - GMBUS type - 50ns at 500MHz cdclk All  

01b 125 ns 1/4 2X bit clock divider value - 125ns All  

10b 62.5 ns 1/8 2X bit clock divider value - 62.5ns All  

11b 31.125 ns 1/16 2X bit clock divider value - 31.125ns All 

9

0b

RW

Project: All Format: 

8

0b

RW

Project: All  

Default Value: 0b  

Value Name Description Project  

0b Okay Multiple edges in window is okay All  

1b Error Multiple edges in window is an error All 

7:6

0b

RW

Readback of bit clock divide field gives the 

error type io_aux_data_syncro and aux_io_data and sm_noa[3:0] and 

clkregen_baddatastop and mdec_toomuchdata and mdec_notbytealign and 

mdec_multiedgeinwin and  

Input data Output data Control state machine Error - bad STOP at end of data Error - 

too much data Error - data not byte aligned Error - multiple edges inside of window 

Error - multiple edges outside of window  

All 

5:0

0b

RW

Project: All Format: