Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

809

LPE Audio Status

Default: 00000000h

15

0b

RW

This R/W bit reflects the state of CP request from the audio unit. When an 

audio CP request has been serviced, it must be reset to 1 by the video software to 

indicate that the CP request has been serviced. 

0 = CP request pending or not ready to receive requests (default) 

1 = CP request ready 

CP_ready bit is programmable through Bit 14 for [DevCL, DevBLC]. 

CP_ready bit is programmable through Bit 15 for [DevCTG].  

Bit 15 Reserved for [DevCL, DevBLC].

14

0b

RW

ELD valid: This bit reflects the state of the ELD data written to the 

ELD RAM. After writing the ELD data, the video software must set this bit to 1 to indicate 

that the ELD data is valid. At audio codec initialization, or on a hotplug event, this bit is 

set to 0 by the video software. This bit is reflected in the audio pin complex widget as 

the ELD valid status bit.0 = ELD data invalid (default, when writing ELD data, set 0 by 

software) 

1 = ELD data valid (Set by video software only) 

ELD bit is programmable through Bit 13 for [DevCL, DevBLC]. 

ELD bit is programmable through Bit 14 for [DevCTG].

13:9

0b

RW

ELD buffer size (read only)10000 = This field reflects the size of the ELD 

buffer in DWORDs 

13:9 reflects ELD buffer size for [DevCTG]. 

12:9 reflects ELD buffer size for [DevCL, DevBLC].

8:5

0b

RW

ELD access address (R/W): Selects the DWORD address for access to 

the ELD buffer (48 bytes). The value wraps back to zero when incremented past the 

max addressing value 0xF. This field change takes effect immediately after being 

written. The read value indicates the current access address.

4

0b

RW

ELD ACK: Acknowledgement from the audio driver that ELD read has 

been completed

3:0

0b

RW

Selects the DWORD address for access to the 

DIP buffers. The value wraps back to zero when it incremented past the max addressing 

value of 0xF. This field change takes effect immediately after being written. The read 

value indicates the current access address.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h