Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

811

Audio HDMI Data Island Packet Data

Default: 00000000h

LPE Audio Configuration

2

0b

RW

This bit is to enable the vucp, PR, ECC to be generated 

in the Azalia way 

0 = Disable Azalia compatible mode on vucp, PR, ECC 

1 = Enable Azalia compatible mode on vucp, PR, ECC

1

0b

RW

When set it allows to fetch sample 128 times 

than the real sample rate to allow a faster drain of sample bufferes.

0

0b

RW

Write 1 to this bit will reset hardware within audio 

unit without needs of reset the full display controller. The FIFO and pointers will be reset 

and audio registers will be reset to default values. Write 0 will put the unit back to idle 

and ready to be programmed again. 

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DA

TA

_ISLAND_P

A

C

K

E

T

_DA

TA

31:0

0b

RW

When read, this returns the current value at the 

location specified in the Video DIP buffer index select and Video DIP RAM access address 

fields. The index used to address the RAM is incremented after each read or write of this 

register. DIP data can be read at any time. Data should be loaded into the RAM before 

enabling the transmission through the DIP type enable bit. Accesses to this register are 

on a per-DWORD basis