Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
840
Datasheet
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FIFO_A_UN
D
ER_RUN_ST
A
TUS
SPRITE
_B_FLIP
_
D
O
NE_INTE
RRU
PT_E
NABLE
CRC_ERROR_E
N
ABLE
CRC_D
O
NE
_ENA
BLE
G
M
B
U
S
_
EV
E
N
T
_
ENA
B
LE
PL
ANE_A
_
FLIP_D
ONE_INTE
RRUP
T
_E
NABLE
VER
T
ICAL_SYN
C_INTERRU
PT_ENABLE
D
ISPLA
Y_LINE_COMP
A
RE_E
NABLE
DP
ST_E
VENT_E
NABLE
SPRITE_A_FLIP
_
D
O
NE_INTE
RRU
PT_E
NABLE
ODD_FIE
LD_INTERR
UPT_E
V
ENT_E
N
ABLE
E
V
E
N
_FIE
LD_INTERR
U
PT_E
VENT_E
NABLE
PE
R
FORMANC
E_C
O
UNTER_E
V
ENT_E
N
ABLE
S
TAR
T_OF_VE
R
TICAL
_
B
LANK_INTE
RRUPT_E
NABLE
FRAM
E
S
TA
R
T
_INTE
RRU
PT_E
NABLE
P
IPE_A_HORIZ
ONT
A
L_
B
LANK_INTE
RRU
PT_E
NABLE
SPRIT
E
_B_FLIP_DONE_INTE
RRUP
T
_ST
A
TUS
SPRITE
_A_FLIP_DONE_INTE
RRUP
T
_ST
A
TUS
CRC_ERROR_INTE
RRUP
T
_ST
A
TUS
CRC_D
O
NE
_INTERRUP
T
_S
TA
TUS
GMBUS_INTE
RRUPT
_ST
A
TUS
PL
ANE
_
A_FLIP
_DONE_INTE
RRU
PT
_ST
A
TU
S
VER
T
IC
AL_SY
N
C_INTE
RRU
PT
_ST
A
TU
S
D
ISPLA
Y_LINE_COMP
A
RE_INTE
RRUP
T
_ST
A
TUS
DP
ST_E
VENT
_ST
A
TU
S
PIP
E
_A_P
ANEL_SE
LF_REFRE
S
H_ST
A
T
US
OD
D_FIELD_INTE
RRUPT
_ST
A
TUS
EVEN_FIELD_INTE
RRUP
T
_ST
A
TUS
PERFO
R
MANC
E
_
MONIT
O
R_EV
ENT_INTE
RRU
PT
ST
AR
T_OF_V
ER
T
ICA
L_BLANK_INTE
RRU
PT
_ST
A
TU
S
FRAMEST
A
R
T
_INTE
RRUP
T
_ST
A
TUS
PIP
E
_A_HORIZ
ON
TA
L_BLANK
_
ST
A
T
US
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW/1C
FIFO_A_UNDER_RUN_STATUS:
Set when a pipe A FIFO under-run occurs, cleared by
a write of a 1. An underrun has occurred on an attempt to pop an empty FIFO. This does
not feed into the first line interrupt status register. This will occur naturally during mode
changes, to be useful, it should be cleared after a mode change has occurred. This bit is
only valid after Pipe A has been completely configured.
1 = FIFO A Underflow occurred
0 = FIFO A Underflow did not occur
AccessType: One to Clear
30
0b
RW
SPRITE_B_FLIP_DONE_INTERRUPT_ENABLE:
This will enable the consideration of
the Sprite B flip done interrupt status bit in the first line interrupt logic
0 = Sprite B Flip Done Interrupt Disabled
1 = Sprite B Flip Done Interrupt Enabled
29
0b
RW
CRC_ERROR_ENABLE:
This will enable the consideration of the CRC error status bit in
the first line interrupt/status logic.
0 = CRC Error Detect Disabled
1 = CRC Error Detect Enabled
28
0b
RW
CRC_DONE_ENABLE:
This will enable the consideration of the CRC error status bit in
the first line interrupt/status logic.
0 = CRC Done Detect Disabled
1 = CRC Done Detect Enabled
27
0b
RW
GMBUS_EVENT_ENABLE:
This will enable the use of the GMBUS interrupt status bit in
the first line interrupt/status logic.
0 = No GMBUS event enabled
1 = GMBUS event enabled
26
0b
RW
PLANE_A_FLIP_DONE_INTERRUPT_ENABLE:
This will enable the consideration of
the Plane A flip done interrupt status bit in the first line interrupt logic
0 = Plane A flip done Interrupt/Status Disabled
1 = Plane A flip done Interrupt/Status Enabled
25
0b
RW
VERTICAL_SYNC_INTERRUPT_ENABLE:
This will enable the consideration of the
vertical sync interrupt status bit in the first line interrupt logic.
0 = Vertical Sync Interrupt/Status Disabled
1 = Vertical Sync Interrupt/Status Enabled
24
0b
RW
DISPLAY_LINE_COMPARE_ENABLE:
This will enable the consideration of the line
compare interrupt status bit in the first line interrupt/status logic.
0 = Display Line Compare Interrupt/Status Disabled
1 = Display Line Compare Interrupt/Status Enabled