Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

841

23

0b

RW

[DevCL, DevCTG, DevCDV]: This interrupt is generated by the 

DPST logic.  

0 = No DPST event enabled 

1 = DPST event enabled

22

0b

RW

This will enable the consideration of 

the Sprite A flip done interrupt status bit in the first line interrupt logic 

0 = Sprite A Flip Done Interrupt Disabled 

1 = Sprite A Flip Done Interrupt Enabled

21

0b

RW

This bit should only be used when this 

pipe is in an interlaced display timing. 

0 = Odd Field Event disable 

1 = Odd Field Event enable

20

0b

RW

This bit should only be used when this 

pipe is in an interlaced display timing. 

0 = Even field Event disable 

1 = Even field Event enable

19

0b

RW

perfomance counter event enable

18

0b

RW

This will enable the 

consideration of the start of vertical blank interrupt status bit in the first line interrupt/

status logic. 

0 = Start of Vertical Blank Interrupt/Status Disabled 

1 = Start of Vertical Blank Interrupt/Status Enabled

17

0b

RW

This will enable the consideration of the vertical 

blank interrupt status bit in the first line interrupt/status logic. 

0 = Vertical Blank Interrupt/Status Disabled 

1 = Vertical Blank Interrupt/Status Enabled

16

0b

RW

: This will enable the 

consideration of the start of horizontal blank interrupt status bit in the first line 

interrupt/status logic0 = Start of Horizontal Blank Interrupt/Status Disabled 

1 = Start of Horizontal Blank Interrupt/Status Enabled

15

0b

RW/1C

MMIO Flip Event is completed on 

Sprite B 

0 = Sprite B Flip Not Done 

1 = Sprite B Flip Done 

AccessType: One to Clear

14

0b

RW/1C

MMIO Flip Event is completed on 

Sprite A 

0 = Sprite A Flip Not Done 

1 = Sprite A Flip Done  

AccessType: One to Clear

13

0b

RW/1C

This sticky status bit is set when a Pipe A CRC 

error is detected. It is cleared by a write of a one. For this bit to be meaningful, the pipe 

and pixel clock should be enabled and running. 

0 = No CRC error has occurred 

1 = CRC Error Detected  

AccessType: One to Clear

12

0b

RW/1C

This sticky status bit is set when Pipe A CRC 

calculation and compare are complete. It is cleared by a write of a one. For this bit to be 

meaningful, the pipe and pixel clock should be enabled and running. 

0 = CRC Not Done 

1 = CRC Done  

AccessType: One to Clear

11

0b

RW/1C

This status bit will be set on a GMBUS event. To use 

this bit in a polling manner, clear the bit by writing a one to it followed by the polling 

loop waiting for it to become set. 

0 = GMBUS event has not occurred 

1 = GMBUS event has occurred  

AccessType: One to Clear