Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

851

Display FIFO Watermark Control 3

Default: 00000000h

7:0

00001111b

RW

Number in 

64Bs of space in FIFO above which the Display Sprite A Stream will generate requests to 

Memory DevBW, DevCL] Display Plane C FIFO Watermark. Number in 64Bs of space in 

FIFO above which the Display C Stream will generate requests to Memory  

(Value should be as recommended in the high priority bandwidth analysis spreadsheet).  

[DevBW, DevCL, DevCDV] Always program to 8.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

E

N

A

B

LE_HPLL_OFF_DURING_

S

ELF_RE

FRESH

RES

E

RVE

D

CURSOR_FIFO_SELF_RE

FRESH_W

A

T

ER

M

A

RK

RES

E

RV

ED_1

H

P

LL

_

S

ELF_RE

FRESH

_

C

U

RS

OR_W

A

T

ER

M

A

RK

RES

E

RVE

D

_

HPLL_SE

LF_REFRE

SH_DISPLA

Y

_W

A

T

ER

M

A

RK

31

0b

RW

. 0 = Disabled 

1 = Enabled 

[DevCL] This bit may be enabled only if the BLC_PWM_CTL duty cycle register offset 

(0x61254) is programmed to 100% and non-legacy backlight is enabled. This restriction 

does not apply when I2C is used for back light modulation. 

[DevCL] When one or more display pipes are enabled, this bit should be disabled before 

accessing the 6XXXh MMIO register address space. Software must follow these steps: 

disable this bit (if enabled and one display pipe is enabled) 

wait for next vblank (switch from hrawclk back to cdclk will occur) 

access the 6XXXh address space as needed 

re-enable this bit  

Note that the wait on next vblank step requires an enabled display pipe.

30

0b

RW

: MBZ