Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

858

Datasheet

Display FIFO WM High Order

Default: 00000000h

11:9

0b

RW

Reserved.

8

1b

RW

This field is the high order bits for Sprite C Start 

pointer. Combinbed with lower order 8-bit Sprite C Start pointer, this field selects the 

end of the ram used for display B and the start of the RAM for Sprite C. If display B is 

unused, this field can be set to zero. The value should never exceed the size of the RAM 

(TOTALSIZE). The size of the display B FIFO will be (Sprite C START)*64 bytes.

7:5

0b

RW

Reserved.

4

1b

RW

This field is the high order bits for Sprite B Start 

pointer. Combinbed with lower order 8-bit Sprite B Start pointer, this field selects the 

end of the ram used for Sprite A and the start of the RAM for Sprite B. If sprite A is 

unused, this field can be set to the same value as Sprite A START. If Sprite B is unused, 

this field can be set to TOTALSIZE-1. It must be programmed to a number greater than 

or equal to the value in Sprite A START and less than the total size of the RAM 

(TOTALSIZE). The size of the Sprite A FIFO will be (Sprite B START-Sprite A START)*64. 

The size of the Sprite B FIFO will be (TOTALSIZE-Sprite B START-1) *64 bytes. 

[DevBLC and DevCTG]: Reserved: Write as zero.

3:1

0b

RW

Reserved.

0

1b

RW

This field is the high order bits for Sprite A Start 

pointer. Combinbed with lower order 8-bit Sprite A Start pointer, this field selects the 

end of the ram used for display A and the start of the RAM for Sprite A. If display A is 

unused, this field can be set to zero. The value should never exceed the size of the RAM 

(TOTALSIZE). The size of the display A FIFO will be (Sprite A START)*64 bytes.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h