Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

897

16

0b

RW

Freeses hpdb_intr_fix, hpdc_intr_fix, hpdd_intr_fix

15

0b

RW

Reserved.

14

0b

RW

1: Lanes considered as ready for normal 

operation 

0: usual operation: Lanes readiness indications arrived from DPIO SEG outputs 

[DevVLVP]: Reserved

13

0b

RW

1: Lanes considered as ready for normal 

operation 

0: usual operation: Lanes readiness indications arrived from DPIO SEG outputs 

[DevVLVP]: Reserved

12

0b

RW

1: Both mPHY DPLLs considered as OK ('1'). Lanes can be 

enabled. 

0: usual operation: DPLL readiness indications arrived from DPIO SEG outputs 

[DevVLVP]: Reserved

11

0b

RW

This bit is to enable viewing critical control signals that 

were added as a result of Cantiga B0 Overlay changes. Default = 0. 

(dpr_dps_noa_scaleen) 

0: Non-scaling signals are sent to NOA bus 

1: Scaling signals are sent to the NOA bus

10

0b

RW

This chicken bit bypasses the current logic used for 

calculating the number of requests to make for an asynchronous flip. It will be helpful 

because the current logic is very difficult to validate. 

(dpr_vs_afliptotal_chicken)

9

0b

RW

This chicken bit bypasses the current logic used for 

selecting the proper byte enables. It is intended to address byte enables during 

asynchronous flips, but it was easier to bypass the entire byte-enable circuit instead. 

HSD bug #1932963. (dpr_vs_byteen_chicken)

8

0b

RW

This chicken bit bypasses the current logic used for 

selecting the starting fetch address of an asynchronous flip. HSD bug #1932964. 

(dpr_vs_aflipaddr_chicken)

7:6

0b

RW

When set vsync reset is asserted and when clear no reset is 

asserted. (dprddb_novsyncreset) 

This selects between VRVSYNC and hi-res VSYCN when set with dprvrd_novsyncreset 

also set sync_select novsyncreset. (dprddb_sync_select) 

X0 = No Vsync reset 

01 = VGA vsync or hi-res between Nat and UL mode 

11 = VGA vsync reset in both UL and native

5

0b

RW

C0 ECO1 chicken bit defaulted to fix enable

4

0b

RW

EGLK A5 ECO1 Fix. Read Data Fix For RMBus Protocol. 

vsmunit: Lock Up Issue.

3:2

0b

RW

VGATEST2 issue fix, Stall throttling done 

during horiz_blank and UL mode is asserted. 

(DPRVGA_dpbstall_ul_threshold). 

01: DPB to VGA stall during UL mode

1

0b

RW

When set this bit will disable the sample 

present bits being set in layout 1 mode of Audio. Default is to enable sample present on 

Audio. (DPRAUDM_sample_present_disable) 

vsmunit: FBC/SR Power Fix

0

0b

RW

[DevVLVP] MBZ. This bit si the same as bit 31 in 70450h 

rega_loadcount_crtdetect