Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

899

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DPTPIP

E

B

_CHICKEN_BIT

S

DP

T

P

IPE

A

_CHICKEN_BIT

S

PI

PE

B

C

LK

GA

TEE

N

PIPE

AC

LKG

A

TE

EN

MENC16

M

E

NC_

N

EV

E

R

END

ING

FREQUENCY_WINDOWING

GO

OD_

S

YN

C

SELECT_CDCLK_COUNT_FOR_D

EGLIT

C

H

CH

ICK

E

N_UNGA

TE

CLK

CH

ICKEN

_

MUL

T

IEDG

EERROR

RE

ADBA

C

K

AU

X

D

_G

MBUS_CONNECTION

AUX

C

_G

MBUS_CONNECTION

AU

X

B

_G

MBUS_CONNECTION

31:25

0b

RW

not used [DevVLVP]: Reserved

24:18

0b

RW

not used [DevVLVP]: Reserved

17

0b

RW

Enables reg_pipeBclkgateen_cd reg_pipeBclkgateen_db 

[DevVLVP]: Reserved

16

0b

RW

Enables reg_pipeAclkgateen_cd reg_pipeAclkgateen_da 

[DevVLVP]: Reserved

15

0b

RW

Chicken to cause MENC to output just 16 manchester 0s for sync (otherwise 

26) [DevVLVP]: Reserved

14

0b

RW

Chicken to cause MENC to output neverending sync 0s for 

electrical testing [DevVLVP]: Reserved

13

0b

RW

Chicken to tighten the frequency windowing [DevVLVP]: 

Reserved

12

0b

RW

Chicken to check for only 8 good sync 0s instead of 12 [DevVLVP]: 

Reserved

11:10

0b

RW

11 = 1/16 2X bit clock divider value - 

31.125ns 

10 = 1/8 2X bit clock divider value - 62.5ns 

01 = 1/4 2X bit clock divider value - 125ns 

00 = 25 - GMBUS type 50ns at 500MHz cdclk 

[DevVLVP]: Reserved

9

0b

RW

1 = Ungate clock 

0 = Automatic clock gating 

[DevVLVP]: Reserved

8

0b

RW

1 = Multiple edges in window is an eror 

0 = Multiple edges in window is okay 

[DevVLVP]: Reserved

7:6

0b

RW

11 = Readback of bit clock divide field gives the error type  

01 = Readback gives the recovered clock frequency 

00 = Readback gives the programmed clock frequency 

[DevVLVP]: Reserved

5:4

0b

RW

Selectes gmbus connection for AUXD [DevVLVP]: 

Reserved