Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Power Management
Intel
®
Atom™ Processor E3800 Product Family
90
Datasheet
•
Any internal event that will cause an NMI or SMI_B
•
CPU Pending Break Event (PBE_B)
•
MSI
6.3.4
Processor Core C-States Description
The following state descriptions assume that both threads are in common low power
state.
state.
6.3.4.1
Core C0 State
The normal operating state of a core where code is being executed.
6.3.4.2
Core C1 State
C1 is a low power state entered when a core execute a HLT or MWAIT(C1) instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal
state or the C1 state. See the Intel
state or the C1 state. See the Intel
®
64 and IA-32 Architecture Software Developer’s
Manual, Volume 3A/3B: System Programmer’s Guide for more information.
While a core is in C1 state, it processes bus snoops and snoops from other threads.
6.3.4.3
Core C6 State
Individual core can enter the C6 state by initiating a P_LVL3 I/O read or an MWAIT(C6)
instruction. Before entering core C6, the core will save its architectural state to a
dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts.
During exit, the core is powered on and its architectural state is restored.
instruction. Before entering core C6, the core will save its architectural state to a
dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts.
During exit, the core is powered on and its architectural state is restored.
There are various types of C-state:
Figure 10. Idle Power Management Breakdown of the Processor Cores
Processor Package State
Core 1 State
Core 0 State