Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

936

Datasheet

Software Flag Registers

22

0b

RW

This determines which palette the VGA palette 

writes will have as a destination.  

One or both palettes can be the destination. If both are disabled, writes will not affect 

the palette RAM contents.  

0 = VGA palette writes will update Palette A (default). 

1 = VGA palette writes will not update Palette A 

VGA palette writes are writes to I/O address 0x3C9h.

21

0b

RW

This determines which palette 

the VGA palette writes will have as a destination. One or both palettes can be the 

destination. If both are disabled, writes will not affect the palette RAM contents.  

0 = VGA palette writes will update Palette B (default). 

1 = VGA palette writes will not update Palette B 

VGA palette writes are writes to I/O address 0x3C9h. 

20

0b

RW

This bit only affects reads and writes to 

the palette through VGA I/O addresses. In the 6-bit mode, the 8-bits of data are shifted 

up two bits on the write (upper two bits are lost) and shifted two bits down on the read. 

It provides backward compatibility for original VGA programs (in it s default state) as 

well as VESA VBE support for 8-bit palette. It does not affect palette accesses through 

the palette register MMIO path. 

0 = 6-bit DAC (default). 

1 = 8-bit DAC.

19

0b

RW

0 = Pass VGA data through the palette for 

translation (Normal Operation) 

1 = Bypass the palette for allowing testing without loading palette both VGA and popup 

data will bypass the palette in this mode.

18

0b

RW

Prevents DOS applications from setting the VGA display into a 

real 9-dot per character operation mode, instead the device emulates that using 8-dots 

per character. This is intended to provide VGA compatibility on DVI type connectors and 

integrated panels where there would otherwise not be room for the 720 horizontal pixels 

or 1440 pixels when horizontally doubled. The VGA register bit SR01(0) functionality is 

disabled. VGA panning control handles the pseudo 9-dot mode when both this bit is set 

and SR01(0) is clear. 

0 = Enable use of 9-dot enable bit in VGA registers 

1 = Ignore the 9-dot per character bit and always use 8

17

0b

RW

Reserved.

16:8

0b

RW

Software must preserve the contents of these bits.

7:6

0b

RW

Controls the VGA text mode blink duty cycle relative to the 

cursor blink duty cycle. 

00 = 100% Duty Cycle, Full Cursor Rate (Default) 

01 = 25% Duty Cycle, Cursor Rate 

10 = 50% Duty Cycle, Cursor Rate 

11 = 75% Duty Cycle, Cursor Rate

5:0

0b

RW

Controls the VGA blink rate in terms of the number of VSYNCs 

per on/off cycle. These bits are programmed with the (VSYNCs/cycle)/2-1. The proper 

programming of this register is determined by the VSYNC rate that the display requires 

when in a VGA display mode.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h