Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

965

Sprite B Linear Offset Register

Default: 00000000h

14:11

0b

RW

Reserved.

10

0b

RW

This bit indicates that the Sprite B surface data is in tiled memory. 

The tile pitch is specified in bytes in the DSPCSTRIDE register. Only X tiling is supported 

for display surfaces. 

When this bit is set, it affects the hardware interpretation of the DSPCTILEOFF, 

DSPCLINOFF, and DSPCSURFADDR registers. 

0 = Sprite B surface uses linear memory 

1 = Sprite B surface uses X-tiled memory

9:3

0b

RW

Write as zero

2

0b

RW

This bit will force the Sprite B plane to be on the bottom of the Z 

order. If the plane is marked as trusted, it only applies to the Z order of the trusted 

planes. 

0 = Sprite B Z order is determined by the other control bits 

1 = Sprite B is forced to be on the bottom of the Z order.

1

0b

RW

Reserved.

0

0b

RW

With Sprite A and B z-order, bottom control bits, Sprite B plane 

is placed in a specific z-order among other planes in pipe A. 

Display Pipe A Z-orders 

SA 

zorderSA 

bottomSB 

zorderSB 

bottomResulting Pipe Z-order (from bottom to top)Source Keying 

0000PA SA SB CAPA in Black 

1000PA SB SA CAPA in Black 

0001SB PA SA CAuse src keying on SB 

0011SB PA SA CAuse src keying on SB 

1001SB SA PA CAuse src keying on SA 

1011SB SA PA CAuse src keying on SA 

0100SA PA SB CAuse src keying on SA 

1100SA PA SB CAuse src keying on SA 

0110SA SB PA CAuse src keying on SB 

1110SA SB PA CAuse src keying on SB 

0: Sprite B z-order is disabled 

1: Sprite B z-order is enabled

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h