Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1989
27
0h
RW
Aggressive Slumber Partial (ASP):
When set to 1, and the ALPE bit is set, the HBA
shall aggressively enter Slumber state when it clears a bit in the PxCI or PxSACT
register and the register values are 0h. When cleared, and the ALPE bit is set, the HBA
will aggressively enter Partial state when it clears a bit in the PxCI or PxSACT register
and the register values are both 0h. If CAP.SALP is cleard to 0, software shall treat this
bit as reserved.
26
0h
RW
Aggressive Link Power Management Enable (ALPE):
When set, the HBA will
aggressively enter a lower link power state (Partial or Slumber) based upon the setting
of the ASP bit.
25
0h
RW
Drive LED on ATAPI Enable (DLAE):
When set, the HBA will drive the LED pin active
for commands regardless of the state of PxCMD.ATAPI. When cleared, the HBA will only
drive the LED pin active for commands if PxCMD.ATAPI is set to 0. This bit is set by
software
24
0h
RW
Device is ATAPI (ATAPI):
When set, the connected device is an ATAPI device. This bit
is used by the HBA to control whether or not to generate the desktop LED when
commands are active.
23
0h
RW
Automatic Partial to Slumber Transitions Enabled (APSTE):
When set to 1, the
HBA may perform Automatic Partial to Slumber Transitions. When cleared to 0 - the port
shall not perform Automatic Partial to Slumber Transitions. Software shall only set this
bit to 1 - if CAP2.APST is set to 1; if CAP2.APST is cleared to 0 - software shall treat this
bit as reserved.
22
0h
RO
FIS-based Switching Capable Port (FBSCP):
The SATA controller does not support
FIS-Based Switching.
21
0h
RW/O
External SATA Port (ESP):
When set to 1, indicates that this port is routed externally
and will be used with an external SATA device. When set to 1, CAP.SXS must also be set
to 1. When cleared (0), indicates that this port is not routed externally and supports
internal SATA devices only. If ESP is set to 1, then the port may experience hot plug
events.
20
0h
RO
Cold Presence Detection (CPD):
The SATA controller does not support cold presence
detect.
19
0h
RW/O
Mechanical Presence Switch Attached to Port (MPSP):
If set to 1, the platform
supports a mechanical presence switch attached to this port. If cleared to 0, the
platform does not support a mechanical presence switch attached to this port.
18
0h
RW/O
Hot Plug Capable Port (HPCP):
This indicates whether this port is connected to a
device which can be hot plugged. SATA by definition is hot-pluggable, but not all
platforms are constructed to allow the device to be removed (it may be screwed into the
chassis, for example). This bit can be used by system software to indicate a feature
such as eject device to the end-user.
17
0h
RO
Port Multiplier Attached (PMA):
Not supported
16
0b
RO
RSVD0:
Reserved
15
0h
RO
Command List Running (CR):
When this bit is set it indicates that the command list
DMA engine for the port is running.
14
0h
RO
FIS Receive Running (FR):
When this bit is set it indicates that the FIS Receive DMA
engine for the port is running.
13
0h
RO
Mechanical Presence Switch State (MPSS):
The MPSS bit reports the state of a
mechanical presence switch attached to this port. If CAP.SMPS is set to 1 and the
mechanical presence switch is closed then this bit is cleared to 0. If CAP.SMPS is set to 1
and the mechanical presence switch is open then this bit is set to 1. If CAP.SMPS is set
to 0 then this bit is cleared to 0. Software should only use this bit if both CAP.SMPS and
PxCMD.MPSP are set to 1.
Bit
Range
Default &
Access
Description