Nxp Semiconductors LPC2917 User Manual

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

[1]

All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at T

amb

= 125 

°C on wafer 

level. Cased products are tested at T

amb

= 25 

°C (final testing). Both pre-testing and final testing use correlated test conditions to cover 

the specified temperature and power-supply voltage range.

[2]

Leakage current is exponential to temperature; worst-case value is at 125 C Tvj. All clocks off. Analog modules and FLASH powered 
down.

[3]

For Port 0, pin 0 to pin 15 add maximum 1.5 pF for input capacitance to ADC. For Port 0, pin 16 to pin 31 add maximum 1.0 pF for input 
capacitance to ADC.

[4]

This value is the minimum drive capability. Maximum short-circuit output current is 33 mA (drive HIGH-level, shorted to ground) or 
−38 mA. (drive LOW-level, shorted to V

DD(IO)

). The device will be damaged if multiple outputs are shorted.

[5]

C

xtal

 is crystal load capacitance and C

ext

 are the two external load capacitors.

[6]

The power-up reset has a time filter: V

DD(CORE)

 must be above V

trip(high)

 for 2 

μs before reset is de-asserted; V

DD(CORE)

 must be below 

V

trip(low)

 for 11

μs before internal reset is asserted.

[7]

Not 5 V-tolerant when pull-up is on.

[8]

For I/O Port 0, the maximum input voltage is defined by V

I(ADC)

.

[9]

This parameter is not part of production testing or final testing, hence only a typical value is stated. Maximum and minimum values are 
based on simulation results.

 

R

s(xtal)

Crystal series resistance.

f

osc

= 10 MHz to 15 MHz

C

xtal

= 10 pF; 

C

ext

= 18 pF

-

-

160

Ω

C

xtal

= 20 pF; 

C

ext

= 39 pF

-

-

60

Ω

f

osc

= 15 MHz to 20 MHz

C

xtal

= 10 pF; 

C

ext

= 18 pF

-

-

80

Ω

C

i

Input capacitance of 
XIN_OSC.

-

2

pF

V

trip(high)

High trip-level voltage.

1.2

1.4

1.6

V

V

trip(low)

Low trip-level voltage.

1.1

1.3

1.5

V

V

trip(dif)

Difference between high 
and low trip-level 
voltages.

50

120

180

mV

°

°

−

°

t

THL

HIGH-to-LOW 
transition time.

C

L

= 30 pF

4

-

13.8

ns

t

TLH

LOW-to-HIGH 
transition time.

C

L

= 30 pF

4

-

13.8

ns