SMSC LAN9420i Manual De Usuario
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
89
Revision 1.22 (09-25-08)
DATASHEET
4.2.3
Interrupt Status Register (INT_STS)
This register contains the current status of the generated interrupts. Some of these interrupts are also
cleared through this register.
cleared through this register.
Offset:
00C8h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
RESERVED
RO
-
15
Software Interrupt (SW_INT)
This bit latches high upon the SW_INT_EN bit toggling from a 0 to 1. The
interrupt is cleared by writing a ‘1’. Writing ‘0’ has no effect.
This bit latches high upon the SW_INT_EN bit toggling from a 0 to 1. The
interrupt is cleared by writing a ‘1’. Writing ‘0’ has no effect.
R/WC
0b
14
RESERVED
RO
-
13
Master Bus Error Interrupt (MBERR_INT)
When set, indicates DMA Controller has detected an error during descriptor
read, or during a transmit data read operation. The interrupt is cleared by
writing a ‘1’ to this bit. Writing a ‘0’ has no effect.
When set, indicates DMA Controller has detected an error during descriptor
read, or during a transmit data read operation. The interrupt is cleared by
writing a ‘1’ to this bit. Writing a ‘0’ has no effect.
To guarantee a clean recovery from a MBERR_INT condition, a software
reset must be performed by setting the
reset must be performed by setting the
. Alternatively, the condition may be
cleared by a hardware reset.
R/WC
0b
12
Slave Bus Error Interrupt (SBERR_INT)
When set, indicates that the PCI Target Interface has detected an error
when the Host attempted to access the LAN9420/LAN9420i CSR. The
interrupt is cleared by writing a ‘1’ to this bit. Writing a ‘0’ has no effect.
When set, indicates that the PCI Target Interface has detected an error
when the Host attempted to access the LAN9420/LAN9420i CSR. The
interrupt is cleared by writing a ‘1’ to this bit. Writing a ‘0’ has no effect.
To guarantee a clean recovery from a SBERR_INT condition, a software
reset must be performed by setting the
reset must be performed by setting the
. Alternatively, the condition may be
cleared by a hardware reset
R/WC
0b
11:7
RESERVED
RO
-
6:4
GPIO [2:0] (GPIOx_INT)
Interrupts are generated from the GPIO’s. These interrupts are configured
through the GPIO_CFG register. Refer to
Interrupts are generated from the GPIO’s. These interrupts are configured
through the GPIO_CFG register. Refer to
information. These interrupts are cleared by writing a ‘1’ to the
corresponding bits. Writing ‘0’ has no effect.
corresponding bits. Writing ‘0’ has no effect.
R/WC
000b
3
GP Timer (GPT_INT)
This interrupt is issued when the General Purpose Timer wraps from
maximum count to zero. This interrupt is cleared by writing a ‘1’ to this bit.
Writing ‘0’ has no effect.
This interrupt is issued when the General Purpose Timer wraps from
maximum count to zero. This interrupt is cleared by writing a ‘1’ to this bit.
Writing ‘0’ has no effect.
R/WC
0b
2
PHY Interrupt (PHY_INT)
Indicates assertion of the PHY Interrupt. The PHY interrupt is cleared by
clearing the interrupt source in the PHY Interrupt Status Register. Refer to
Indicates assertion of the PHY Interrupt. The PHY interrupt is cleared by
clearing the interrupt source in the PHY Interrupt Status Register. Refer to
for more information
on this interrupt. Writing to this bit has no effect.
RO
0b