SMSC LAN9420i Manual De Usuario
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
91
Revision 1.22 (09-25-08)
DATASHEET
4.2.4
Interrupt Configuration Register (INT_CFG)
This register configures and monitors the interrupt (IRQ) signal.
Control of the de-assertion interval for the IRQ is also included. The de-assertion interval is the
minimum time the IRQ will remain de-asserted after it has been asserted and cleared. After this time
period has elapsed, the IRQ will be asserted if the interrupt is active. This interval begins counting
when interrupt sources have been cleared from the asserted state. Refer to
minimum time the IRQ will remain de-asserted after it has been asserted and cleared. After this time
period has elapsed, the IRQ will be asserted if the interrupt is active. This interval begins counting
when interrupt sources have been cleared from the asserted state. Refer to
for more information on the Interrupt Controller.
Offset:
00CCh
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:20
RESERVED
RO
-
19
Master Interrupt (IRQ_INT)
This read-only bit indicates the state of the IRQ line. When set high, one of
the enabled interrupts is currently active. This bit will respond to the
associated interrupts regardless of the IRQ_EN field. This bit is not affected
by the setting of the INT_DEAS field.
This read-only bit indicates the state of the IRQ line. When set high, one of
the enabled interrupts is currently active. This bit will respond to the
associated interrupts regardless of the IRQ_EN field. This bit is not affected
by the setting of the INT_DEAS field.
RO
0b
18
IRQ Enable (IRQ_EN)
When cleared, the IRQ output to the PCIB is disabled and will be
permanently de-asserted. When set, the IRQ output functions normally.
When cleared, the IRQ output to the PCIB is disabled and will be
permanently de-asserted. When set, the IRQ output functions normally.
R/W
0b
17:10
RESERVED
RO
-
9
Interrupt De-assertion Interval Clear (INT_DEAS_CLR)
Writing a one to this register clears the de-assertion counter in the Interrupt
Controller, thus causing a new de-assertion interval to begin (regardless of
whether or not the Interrupt Controller is currently in an active de-assertion
interval).
Writing a one to this register clears the de-assertion counter in the Interrupt
Controller, thus causing a new de-assertion interval to begin (regardless of
whether or not the Interrupt Controller is currently in an active de-assertion
interval).
R/W/SC
0b
8
Interrupt De-assertion Status (INT_DEAS_STS)
When set, this bit indicates that the INT_DEAS is currently in a de-assertion
interval, and any interrupts (as indicated by the IRQ_INT and INT_EN bits)
will not be delivered to the IRQ. When cleared, the INT_DEAS is currently
not in a de-assertion interval, and enabled interrupts will be delivered to the
IRQ.
When set, this bit indicates that the INT_DEAS is currently in a de-assertion
interval, and any interrupts (as indicated by the IRQ_INT and INT_EN bits)
will not be delivered to the IRQ. When cleared, the INT_DEAS is currently
not in a de-assertion interval, and enabled interrupts will be delivered to the
IRQ.
RO
0b
7:0
Interrupt De-assertion Interval (INT_DEAS)
This field determines the interrupt de-assertion interval for the IRQ in
multiples of 10 microseconds.
This field determines the interrupt de-assertion interval for the IRQ in
multiples of 10 microseconds.
Writing zeros to this field disables the INT_DEAS interval and resets the
interval counter. Any pending interrupts are then issued. If a new, non-zero
value is written to the INT_DEAS field, any subsequent interrupts will obey
the new setting.
interval counter. Any pending interrupts are then issued. If a new, non-zero
value is written to the INT_DEAS field, any subsequent interrupts will obey
the new setting.
Note:
The interrupt de-assertion interval does not apply to the wake
interrupt.
interrupt.
R/W
00h