Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Fiche De Données

Codes de produits
AT91SAM9N12-EK
Page de 1104
987
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
44.7.16 Base Layer Channel Disable Register
Name: 
LCDC_BASECHDR
Address:
0xF8038044
Access: 
Write-only
Reset: 
0x00000000
• CHDIS: Channel Disable Register
When set to one this field disables the layer at the end of the current frame. The frame is completed.
• CHRST: Channel Reset Register 
When set to one this field resets the layer immediately. The frame is aborted.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
CHRST
7
6
5
4
3
2
1
0
CHDIS