Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

Product codes
AT91SAM9N12-EK
Page of 1104
987
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
44.7.16 Base Layer Channel Disable Register
Name: 
LCDC_BASECHDR
Address:
0xF8038044
Access: 
Write-only
Reset: 
0x00000000
• CHDIS: Channel Disable Register
When set to one this field disables the layer at the end of the current frame. The frame is completed.
• CHRST: Channel Reset Register 
When set to one this field resets the layer immediately. The frame is aborted.
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CHRST
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CHDIS