Manuels d'utilisation pour Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD

Table des matières

• Description

  1
• Features

  2
• 1. Configuration Summary

  4
• 2. Block Diagram

  6
• 3. Signal Description

  13
• 4. Package and Pinout

  17
  • 4.1 100-lead Packages and Pinouts

    17
    • 4.1.1 100-lead LQFP Package Outline

      17
    • 4.1.2 100-ball TFBGA Package Outline

      17
    • 4.1.3 100-ball VFBGA Package Outline

      18
    • 4.1.4 100-lead LQFP Pinout

      19
    • 4.1.5 100-ball TFBGA Pinout

      20
    • 4.1.6 100-ball VFBGA Pinout

      21
  • 4.2 64-lead Packages and Pinouts

    22
    • 4.2.1 64-lead LQFP Package Outline

      22
    • 4.2.2 64-lead QFN Package Outline

      22
    • 4.2.3 64-ball WLCSP Package Outline

      23
    • 4.2.4 64-lead LQFP and QFN Pinout

      23
    • 4.2.5 64-ball WLCSP Pinout

      24
  • 4.3 48-lead Packages and Pinouts

    25
    • 4.3.1 48-lead LQFP Package Outline

      25
    • 4.3.2 48-lead QFN Package Outline

      25
    • 4.3.3 48-lead LQFP and QFN Pinout

      26
• 5. Power Considerations

  27
  • 5.1 Power Supplies

    27
  • 5.2 Voltage Regulator

    27
  • 5.3 Typical Powering Schematics

    28
  • 5.4 Active Mode

    29
  • 5.5 Low-power Modes

    29
    • 5.5.1 Backup Mode

      30
    • 5.5.2 Wait Mode

      30
    • 5.5.3 Sleep Mode

      31
    • 5.5.4 Low-power Mode Summary Table

      31
  • 5.6 Wake-up Sources

    33
  • 5.7 Fast Start-up

    33
• 6. Input/Output Lines

  34
  • 6.1 General Purpose I/O Lines

    34
  • 6.2 System I/O Lines

    34
    • 6.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins

      35
  • 6.3 Test Pin

    35
  • 6.4 NRST Pin

    36
  • 6.5 ERASE Pin

    36
  • 6.6 Anti-tamper Pins/Low-power Tamper Detection

    36
• 7. Product Mapping

  37
• 8. Memories

  38
  • 8.1 Embedded Memories

    38
    • 8.1.1 Internal SRAM

      38
    • 8.1.2 Internal ROM

      38
    • 8.1.3 Embedded Flash

      38
      • 8.1.3.1 Flash Overview

        38
      • 8.1.3.2 Enhanced Embedded Flash Controller

        41
      • 8.1.3.3 Flash Speed

        41
      • 8.1.3.4 Lock Regions

        42
      • 8.1.3.5 Security Bit

        42
      • 8.1.3.6 Calibration Bits

        42
      • 8.1.3.7 Unique Identifier

        43
      • 8.1.3.8 User Signature

        43
      • 8.1.3.9 Fast Flash Programming Interface

        43
      • 8.1.3.10 SAM-BA Boot

        43
      • 8.1.3.11 GPNVM Bits

        43
    • 8.1.4 Boot Strategies

      44
  • 8.2 External Memories

    45
    • 8.2.1 Static Memory Controller

      45
• 9. Real Time Event Management

  46
  • 9.1 Embedded Characteristics

    46
  • 9.2 Real Time Event Mapping List

    47
• 10. System Controller

  48
  • 10.1 System Controller and Peripheral Mapping

    48
  • 10.2 Power-on-Reset, Brownout and Supply Monitor

    48
    • 10.2.1 Power-on-Reset

      48
    • 10.2.2 Brownout Detector on VDDCORE

      48
    • 10.2.3 Supply Monitor on VDDIO

      48
• 11. Peripherals

  49
  • 11.1 Peripheral Identifiers

    49
  • 11.2 Peripheral Signal Multiplexing on I/O Lines

    50
    • 11.2.1 PIO Controller A Multiplexing

      51
    • 11.2.2 PIO Controller B Multiplexing

      52
    • 11.2.3 PIO Controller C Multiplexing

      53
• 12. ARM Cortex-M4 Processor

  54
  • 12.1 Description

    54
    • 12.1.1 System Level Interface

      54
    • 12.1.2 Integrated Configurable Debug

      54
  • 12.2 Embedded Characteristics

    55
  • 12.3 Block Diagram

    55
  • 12.4 Cortex-M4 Models

    56
    • 12.4.1 Programmers Model

      56
      • 12.4.1.1 Processor Modes and Privilege Levels for Software Execution

        56
      • 12.4.1.2 Stacks

        56
      • 12.4.1.3 Core Registers

        57
      • 12.4.1.4 General-purpose Registers

        58
      • 12.4.1.5 Stack Pointer

        58
      • 12.4.1.6 Link Register

        58
      • 12.4.1.7 Program Counter

        58
      • 12.4.1.8 Program Status Register

        59
      • 12.4.1.9 Application Program Status Register

        60
      • 12.4.1.10 Interrupt Program Status Register

        61
      • 12.4.1.11 Execution Program Status Register

        62
      • 12.4.1.12 Exception Mask Registers

        63
      • 12.4.1.13 Priority Mask Register

        64
      • 12.4.1.14 Fault Mask Register

        65
      • 12.4.1.15 Base Priority Mask Register

        66
      • 12.4.1.16 Control Register

        67
      • 12.4.1.17 Exceptions and Interrupts

        68
      • 12.4.1.18 Data Types

        68
      • 12.4.1.19 Cortex Microcontroller Software Interface Standard (CMSIS)

        68
    • 12.4.2 Memory Model

      69
      • 12.4.2.1 Memory Regions, Types and Attributes

        70
      • 12.4.2.2 Memory System Ordering of Memory Accesses

        70
      • 12.4.2.3 Behavior of Memory Accesses

        71
      • 12.4.2.4 Software Ordering of Memory Accesses

        72
      • 12.4.2.5 Bit-banding

        72
      • 12.4.2.6 Memory Endianness

        74
      • 12.4.2.7 Synchronization Primitives

        75
      • 12.4.2.8 Programming Hints for the Synchronization Primitives

        76
    • 12.4.3 Exception Model

      76
      • 12.4.3.1 Exception States

        76
      • 12.4.3.2 Exception Types

        77
      • 12.4.3.3 Exception Handlers

        79
      • 12.4.3.4 Vector Table

        79
      • 12.4.3.5 Exception Priorities

        80
      • 12.4.3.6 Interrupt Priority Grouping

        80
      • 12.4.3.7 Exception Entry and Return

        80
      • 12.4.3.8 Fault Handling

        84
  • 12.5 Power Management

    86
    • 12.5.1 Entering Sleep Mode

      86
      • 12.5.1.1 Wait for Interrupt

        86
      • 12.5.1.2 Wait for Event

        86
      • 12.5.1.3 Sleep-on-exit

        86
    • 12.5.2 Wakeup from Sleep Mode

      86
      • 12.5.2.1 Wakeup from WFI or Sleep-on-exit

        86
      • 12.5.2.2 Wakeup from WFE

        86
      • 12.5.2.3 External Event Input

        87
    • 12.5.3 Power Management Programming Hints

      87
  • 12.6 Cortex-M4 Instruction Set

    88
    • 12.6.1 Instruction Set Summary

      88
    • 12.6.2 CMSIS Functions

      94
    • 12.6.3 Instruction Descriptions

      95
      • 12.6.3.1 Operands

        95
      • 12.6.3.2 Restrictions when Using PC or SP

        95
      • 12.6.3.3 Flexible Second Operand

        96
      • 12.6.3.4 Shift Operations

        97
      • 12.6.3.5 Address Alignment

        99
      • 12.6.3.6 PC-relative Expressions

        99
      • 12.6.3.7 Conditional Execution

        99
      • 12.6.3.8 Instruction Width Selection

        101
    • 12.6.4 Memory Access Instructions

      103
      • 12.6.4.1 ADR

        104
      • 12.6.4.2 LDR and STR, Immediate Offset

        105
      • 12.6.4.3 LDR and STR, Register Offset

        107
      • 12.6.4.4 LDR and STR, Unprivileged

        109
      • 12.6.4.5 LDR, PC-relative

        110
      • 12.6.4.6 LDM and STM

        111
      • 12.6.4.7 PUSH and POP

        113
      • 12.6.4.8 LDREX and STREX

        114
      • 12.6.4.9 CLREX

        115
    • 12.6.5 General Data Processing Instructions

      116
      • 12.6.5.1 ADD, ADC, SUB, SBC, and RSB

        118
      • 12.6.5.2 AND, ORR, EOR, BIC, and ORN

        119
      • 12.6.5.3 ASR, LSL, LSR, ROR, and RRX

        121
      • 12.6.5.4 CLZ

        122
      • 12.6.5.5 CMP and CMN

        123
      • 12.6.5.6 MOV and MVN

        124
      • 12.6.5.7 MOVT

        125
      • 12.6.5.8 REV, REV16, REVSH, and RBIT

        125
      • 12.6.5.9 SADD16 and SADD8

        127
      • 12.6.5.10 SHADD16 and SHADD8

        128
      • 12.6.5.11 SHASX and SHSAX

        129
      • 12.6.5.12 SHSUB16 and SHSUB8

        130
      • 12.6.5.13 SSUB16 and SSUB8

        131
      • 12.6.5.14 SASX and SSAX

        132
      • 12.6.5.15 TST and TEQ

        132
      • 12.6.5.16 UADD16 and UADD8

        133
      • 12.6.5.17 UASX and USAX

        135
      • 12.6.5.18 UHADD16 and UHADD8

        135
      • 12.6.5.19 UHASX and UHSAX

        136
      • 12.6.5.20 UHSUB16 and UHSUB8

        138
      • 12.6.5.21 SEL

        138
      • 12.6.5.22 USAD8

        140
      • 12.6.5.23 USADA8

        141
      • 12.6.5.24 USUB16 and USUB8

        142
    • 12.6.6 Multiply and Divide Instructions

      143
      • 12.6.6.1 MUL, MLA, and MLS

        144
      • 12.6.6.2 UMULL, UMAAL, UMLAL

        144
      • 12.6.6.3 SMLA and SMLAW

        145
      • 12.6.6.4 SMLAD

        147
      • 12.6.6.5 SMLAL and SMLALD

        148
      • 12.6.6.6 SMLSD and SMLSLD

        151
      • 12.6.6.7 SMMLA and SMMLS

        153
      • 12.6.6.8 SMMUL

        154
      • 12.6.6.9 SMUAD and SMUSD

        154
      • 12.6.6.10 SMUL and SMULW

        156
      • 12.6.6.11 UMULL, UMLAL, SMULL, and SMLAL

        158
      • 12.6.6.12 SDIV and UDIV

        159
    • 12.6.7 Saturating Instructions

      160
      • 12.6.7.1 SSAT and USAT

        161
      • 12.6.7.2 SSAT16 and USAT16

        162
      • 12.6.7.3 QADD and QSUB

        162
      • 12.6.7.4 QASX and QSAX

        164
      • 12.6.7.5 QDADD and QDSUB

        166
      • 12.6.7.6 UQASX and UQSAX

        167
      • 12.6.7.7 UQADD and UQSUB

        168
    • 12.6.8 Packing and Unpacking Instructions

      170
      • 12.6.8.1 PKHBT and PKHTB

        171
      • 12.6.8.2 SXT and UXT

        172
      • 12.6.8.3 SXTA and UXTA

        173
    • 12.6.9 Bitfield Instructions

      175
      • 12.6.9.1 BFC and BFI

        176
      • 12.6.9.2 SBFX and UBFX

        177
      • 12.6.9.3 SXT and UXT

        178
    • 12.6.10 Branch and Control Instructions

      179
      • 12.6.10.1 B, BL, BX, and BLX

        180
      • 12.6.10.2 CBZ and CBNZ

        182
      • 12.6.10.3 IT

        183
      • 12.6.10.4 TBB and TBH

        184
    • 12.6.11 Miscellaneous Instructions

      187
      • 12.6.11.1 BKPT

        188
      • 12.6.11.2 CPS

        188
      • 12.6.11.3 DMB

        189
      • 12.6.11.4 DSB

        190
      • 12.6.11.5 ISB

        190
      • 12.6.11.6 MRS

        191
      • 12.6.11.7 MSR

        191
      • 12.6.11.8 NOP

        192
      • 12.6.11.9 SEV

        193
      • 12.6.11.10 SVC

        193
      • 12.6.11.11 WFE

        194
      • 12.6.11.12 WFI

        194
  • 12.7 Cortex-M4 Core Peripherals

    195
    • 12.7.1 Peripherals

      195
    • 12.7.2 Address Map

      195
  • 12.8 Nested Vectored Interrupt Controller (NVIC)

    196
    • 12.8.1 Level-sensitive Interrupts

      196
      • 12.8.1.1 Hardware and Software Control of Interrupts

        196
    • 12.8.2 NVIC Design Hints and Tips

      196
      • 12.8.2.1 NVIC Programming Hints

        197
    • 12.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface

      199
      • 12.8.3.1 Interrupt Set-enable Registers

        200
      • 12.8.3.2 Interrupt Clear-enable Registers

        201
      • 12.8.3.3 Interrupt Set-pending Registers

        202
      • 12.8.3.4 Interrupt Clear-pending Registers

        203
      • 12.8.3.5 Interrupt Active Bit Registers

        204
      • 12.8.3.6 Interrupt Priority Registers

        205
      • 12.8.3.7 Software Trigger Interrupt Register

        206
  • 12.9 System Control Block (SCB)

    207
    • 12.9.1 System Control Block (SCB) User Interface

      208
      • 12.9.1.1 Auxiliary Control Register

        209
      • 12.9.1.2 CPUID Base Register

        210
      • 12.9.1.3 Interrupt Control and State Register

        211
      • 12.9.1.4 Vector Table Offset Register

        213
      • 12.9.1.5 Application Interrupt and Reset Control Register

        214
      • 12.9.1.6 System Control Register

        216
      • 12.9.1.7 Configuration and Control Register

        217
      • 12.9.1.8 System Handler Priority Registers

        219
      • 12.9.1.9 System Handler Priority Register 1

        220
      • 12.9.1.10 System Handler Priority Register 2

        221
      • 12.9.1.11 System Handler Priority Register 3

        222
      • 12.9.1.12 System Handler Control and State Register

        223
      • 12.9.1.13 Configurable Fault Status Register

        225
      • 12.9.1.14 Configurable Fault Status Register (Byte Access)

        229
      • 12.9.1.15 Hard Fault Status Register

        230
      • 12.9.1.16 MemManage Fault Address Register

        231
      • 12.9.1.17 Bus Fault Address Register

        232
  • 12.10 System Timer (SysTick)

    233
    • 12.10.1 System Timer (SysTick) User Interface

      234
      • 12.10.1.1 SysTick Control and Status

        235
      • 12.10.1.2 SysTick Reload Value Registers

        236
      • 12.10.1.3 SysTick Current Value Register

        237
      • 12.10.1.4 SysTick Calibration Value Register

        238
  • 12.11 Memory Protection Unit (MPU)

    239
    • 12.11.1 MPU Access Permission Attributes

      239
      • 12.11.1.1 MPU Mismatch

        241
      • 12.11.1.2 Updating an MPU Region

        241
      • 12.11.1.3 Updating an MPU Region Using Separate Words

        241
      • 12.11.1.4 Updating an MPU Region Using Multi-word Writes

        242
      • 12.11.1.5 Subregions

        243
      • 12.11.1.6 Example of SRD Use

        243
      • 12.11.1.7 MPU Design Hints And Tips

        243
    • 12.11.2 Memory Protection Unit (MPU) User Interface

      245
      • 12.11.2.1 MPU Type Register

        246
      • 12.11.2.2 MPU Control Register

        247
      • 12.11.2.3 MPU Region Number Register

        249
      • 12.11.2.4 MPU Region Base Address Register

        250
      • 12.11.2.5 MPU Region Attribute and Size Register

        251
      • 12.11.2.6 MPU Region Base Address Register Alias 1

        253
      • 12.11.2.7 MPU Region Attribute and Size Register Alias 1

        254
      • 12.11.2.8 MPU Region Base Address Register Alias 2

        256
      • 12.11.2.9 MPU Region Attribute and Size Register Alias 2

        257
      • 12.11.2.10 MPU Region Base Address Register Alias 3

        259
      • 12.11.2.11 MPU Region Attribute and Size Register Alias 3

        260
  • 12.12 Glossary

    262
• 13. Debug and Test Features

  267
  • 13.1 Description

    267
  • 13.2 Embedded Characteristics

    267
  • 13.3 Application Examples

    268
    • 13.3.1 Debug Environment

      268
    • 13.3.2 Test Environment

      268
  • 13.4 Debug and Test Pin Description

    269
  • 13.5 Functional Description

    270
    • 13.5.1 Test Pin

      270
    • 13.5.2 Debug Architecture

      270
    • 13.5.3 Serial Wire/JTAG Debug Port (SWJ-DP)

      270
      • 13.5.3.1 SW-DP and JTAG-DP Selection Mechanism

        271
    • 13.5.4 FPB (Flash Patch Breakpoint)

      271
    • 13.5.5 DWT (Data Watchpoint and Trace)

      271
    • 13.5.6 ITM (Instrumentation Trace Macrocell)

      272
      • 13.5.6.1 How to Configure the ITM

        272
      • 13.5.6.2 Asynchronous Mode

        272
      • 13.5.6.3 5.4.3. How to Configure the TPIU

        273
    • 13.5.7 IEEE® 1149.1 JTAG Boundary Scan

      273
      • 13.5.7.1 JTAG Boundary-scan Register

        273
    • 13.5.8 ID Code Register

      274
• 14. Reset Controller (RSTC)

  275
  • 14.1 Description

    275
  • 14.2 Embedded Characteristics

    275
  • 14.3 Block Diagram

    275
  • 14.4 Functional Description

    276
    • 14.4.1 Reset Controller Overview

      276
    • 14.4.2 NRST Manager

      276
      • 14.4.2.1 NRST Signal or Interrupt

        276
      • 14.4.2.2 NRST External Reset Control

        277
    • 14.4.3 Brownout Manager

      277
    • 14.4.4 Reset States

      277
      • 14.4.4.1 General Reset

        277
      • 14.4.4.2 Backup Reset

        278
      • 14.4.4.3 User Reset

        278
      • 14.4.4.4 Software Reset

        278
      • 14.4.4.5 Watchdog Reset

        279
    • 14.4.5 Reset State Priorities

      280
    • 14.4.6 Reset Controller Status Register

      281
  • 14.5 Reset Controller (RSTC) User Interface

    282
    • 14.5.1 Reset Controller Control Register

      283
    • 14.5.2 Reset Controller Status Register

      284
    • 14.5.3 Reset Controller Mode Register

      285
• 15. Real-time Timer (RTT)

  286
  • 15.1 Description

    286
  • 15.2 Embedded Characteristics

    286
  • 15.3 Block Diagram

    286
  • 15.4 Functional Description

    287
  • 15.5 Real-time Timer (RTT) User Interface

    289
    • 15.5.1 Real-time Timer Mode Register

      290
    • 15.5.2 Real-time Timer Alarm Register

      291
    • 15.5.3 Real-time Timer Value Register

      292
    • 15.5.4 Real-time Timer Status Register

      293
• 16. Real-time Clock (RTC)

  294
  • 16.1 Description

    294
  • 16.2 Embedded Characteristics

    294
  • 16.3 Block Diagram

    295
  • 16.4 Product Dependencies

    295
    • 16.4.1 Power Management

      295
    • 16.4.2 Interrupt

      295
  • 16.5 Functional Description

    295
    • 16.5.1 Reference Clock

      295
    • 16.5.2 Timing

      295
    • 16.5.3 Alarm

      296
    • 16.5.4 Error Checking when Programming

      296
    • 16.5.5 RTC Internal Free Running Counter Error Checking

      296
    • 16.5.6 Updating Time/Calendar

      297
    • 16.5.7 RTC Accurate Clock Calibration

      299
    • 16.5.8 Waveform Generation

      299
  • 16.6 Real-time Clock (RTC) User Interface

    301
    • 16.6.1 RTC Control Register

      302
    • 16.6.2 RTC Mode Register

      303
    • 16.6.3 RTC Time Register

      306
    • 16.6.4 RTC Calendar Register

      307
    • 16.6.5 RTC Time Alarm Register

      308
    • 16.6.6 RTC Calendar Alarm Register

      309
    • 16.6.7 RTC Status Register

      310
    • 16.6.8 RTC Status Clear Command Register

      311
    • 16.6.9 RTC Interrupt Enable Register

      312
    • 16.6.10 RTC Interrupt Disable Register

      313
    • 16.6.11 RTC Interrupt Mask Register

      314
    • 16.6.12 RTC Valid Entry Register

      315
• 17. Watchdog Timer (WDT)

  316
  • 17.1 Description

    316
  • 17.2 Embedded Characteristics

    316
  • 17.3 Block Diagram

    317
  • 17.4 Functional Description

    318
  • 17.5 Watchdog Timer (WDT) User Interface

    320
    • 17.5.1 Watchdog Timer Control Register

      321
    • 17.5.2 Watchdog Timer Mode Register

      322
    • 17.5.3 Watchdog Timer Status Register

      324
• 18. Supply Controller (SUPC)

  325
  • 18.1 Embedded Characteristics

    325
  • 18.2 Block Diagram

    326
  • 18.3 Supply Controller Functional Description

    327
    • 18.3.1 Supply Controller Overview

      327
    • 18.3.2 Slow Clock Generator

      328
    • 18.3.3 Core Voltage Regulator Control/Backup Low-power Mode

      328
    • 18.3.4 Supply Monitor

      328
    • 18.3.5 Backup Power Supply Reset

      329
      • 18.3.5.1 Raising the Backup Power Supply

        329
    • 18.3.6 Core Reset

      330
      • 18.3.6.1 Supply Monitor Reset

        330
      • 18.3.6.2 Brownout Detector Reset

        331
    • 18.3.7 Wake-up Sources

      331
      • 18.3.7.1 Wake-up Inputs

        331
      • 18.3.7.2 Low-power Tamper Detection and Anti-Tampering

        332
      • 18.3.7.3 Clock Alarms

        334
      • 18.3.7.4 Supply Monitor Detection

        334
    • 18.3.8 Register Write Protection

      334
    • 18.3.9 Register Bits in Backup Domain (VDDIO)

      335
  • 18.4 Supply Controller (SUPC) User Interface

    336
    • 18.4.1 System Controller (SYSC) User Interface

      336
    • 18.4.2 Supply Controller (SUPC) User Interface

      336
    • 18.4.3 Supply Controller Control Register

      337
    • 18.4.4 Supply Controller Supply Monitor Mode Register

      338
    • 18.4.5 Supply Controller Mode Register

      339
    • 18.4.6 Supply Controller Wake-up Mode Register

      340
    • 18.4.7 Supply Controller Wake-up Inputs Register

      342
    • 18.4.8 Supply Controller Status Register

      343
    • 18.4.9 System Controller Write Protection Mode Register

      345
• 19. General-Purpose Backup Registers (GPBR)

  346
  • 19.1 Description

    346
  • 19.2 Embedded Characteristics

    346
  • 19.3 General Purpose Backup Registers (GPBR) User Interface

    347
    • 19.3.1 General Purpose Backup Register x

      348
• 20. Enhanced Embedded Flash Controller (EEFC)

  349
  • 20.1 Description

    349
  • 20.2 Embedded Characteristics

    349
  • 20.3 Product Dependencies

    349
    • 20.3.1 Power Management

      349
    • 20.3.2 Interrupt Sources

      349
  • 20.4 Functional Description

    350
    • 20.4.1 Embedded Flash Organization

      350
    • 20.4.2 Read Operations

      351
      • 20.4.2.1 128-bit or 64-bit Access Mode

        351
      • 20.4.2.2 Code Read Optimization

        351
      • 20.4.2.3 Code Loop Optimization

        352
      • 20.4.2.4 Data Read Optimization

        353
    • 20.4.3 Flash Commands

      354
      • 20.4.3.1 Get Flash Descriptor Command

        356
      • 20.4.3.2 Write Commands

        356
      • 20.4.3.3 Erase Commands

        360
      • 20.4.3.4 Lock Bit Protection

        361
      • 20.4.3.5 GPNVM Bit

        362
      • 20.4.3.6 Calibration Bit

        362
      • 20.4.3.7 Security Bit Protection

        363
      • 20.4.3.8 Unique Identifier

        363
      • 20.4.3.9 User Signature

        363
  • 20.5 Enhanced Embedded Flash Controller (EEFC) User Interface

    365
    • 20.5.1 EEFC Flash Mode Register

      366
    • 20.5.2 EEFC Flash Command Register

      367
    • 20.5.3 EEFC Flash Status Register

      369
    • 20.5.4 EEFC Flash Result Register

      370
• 21. Fast Flash Programming Interface (FFPI)

  371
  • 21.1 Description

    371
  • 21.2 Embedded Characteristics

    371
  • 21.3 Parallel Fast Flash Programming

    372
    • 21.3.1 Device Configuration

      372
    • 21.3.2 Signal Names

      373
    • 21.3.3 Entering Programming Mode

      374
    • 21.3.4 Programmer Handshaking

      374
      • 21.3.4.1 Write Handshaking

        374
      • 21.3.4.2 Read Handshaking

        375
    • 21.3.5 Device Operations

      376
      • 21.3.5.1 Flash Read Command

        377
      • 21.3.5.2 Flash Write Command

        377
      • 21.3.5.3 Flash Full Erase Command

        378
      • 21.3.5.4 Flash Lock Commands

        378
      • 21.3.5.5 Flash General-purpose NVM Commands

        378
      • 21.3.5.6 Flash Security Bit Command

        379
      • 21.3.5.7 Memory Write Command

        379
      • 21.3.5.8 Get Version Command

        380
• 22. Cortex-M Cache Controller (CMCC)

  381
  • 22.1 Description

    381
  • 22.2 Embedded Characteristics

    381
  • 22.3 Block Diagram

    382
  • 22.4 Functional Description

    382
    • 22.4.1 Cache Operation

      382
    • 22.4.2 Cache Maintenance

      382
      • 22.4.2.1 Cache Invalidate by Line Operation

        382
      • 22.4.2.2 Cache Invalidate All Operation

        383
    • 22.4.3 Cache Performance Monitoring

      383
  • 22.5 Cortex M Cache Controller (CMCC) User Interface

    384
    • 22.5.1 Cache Controller Type Register

      385
    • 22.5.2 Cache Controller Configuration Register

      387
    • 22.5.3 Cache Controller Control Register

      388
    • 22.5.4 Cache Controller Status Register

      389
    • 22.5.5 Cache Controller Maintenance Register 0

      390
    • 22.5.6 Cache Controller Maintenance Register 1

      391
    • 22.5.7 Cache Controller Monitor Configuration Register

      392
    • 22.5.8 Cache Controller Monitor Enable Register

      393
    • 22.5.9 Cache Controller Monitor Control Register

      394
    • 22.5.10 Cache Controller Monitor Status Register

      395
• 23. Cyclic Redundancy Check Calculation Unit (CRCCU)

  396
  • 23.1 Description

    396
  • 23.2 Embedded Characteristics

    396
  • 23.3 CRCCU Block Diagram

    397
  • 23.4 Product Dependencies

    398
    • 23.4.1 Power Management

      398
    • 23.4.2 Interrupt Source

      398
  • 23.5 CRCCU Functional Description

    399
    • 23.5.1 CRC Calculation Unit

      399
    • 23.5.2 CRC Calculation Unit Operation

      399
  • 23.6 Transfer Control Registers Memory Mapping

    400
    • 23.6.1 Transfer Address Register

      401
    • 23.6.2 Transfer Control Register

      402
    • 23.6.3 Transfer Reference Register

      403
  • 23.7 Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface

    404
    • 23.7.1 CRCCU Descriptor Base Address Register

      405
    • 23.7.2 CRCCU DMA Enable Register

      406
    • 23.7.3 CRCCU DMA Disable Register

      407
    • 23.7.4 CRCCU DMA Status Register

      408
    • 23.7.5 CRCCU DMA Interrupt Enable Register

      409
    • 23.7.6 CRCCU DMA Interrupt Disable Register

      410
    • 23.7.7 CRCCU DMA Interrupt Mask Register

      411
    • 23.7.8 CRCCU DMA Interrupt Status Register

      412
    • 23.7.9 CRCCU Control Register

      413
    • 23.7.10 CRCCU Mode Register

      414
    • 23.7.11 CRCCU Status Register

      415
    • 23.7.12 CRCCU Interrupt Enable Register

      416
    • 23.7.13 CRCCU Interrupt Disable Register

      417
    • 23.7.14 CRCCU Interrupt Mask Register

      418
    • 23.7.15 CRCCU Interrupt Status Register

      419
• 24. Boot Program

  420
  • 24.1 Description

    420
  • 24.2 Hardware and Software Constraints

    420
  • 24.3 Flow Diagram

    420
  • 24.4 Device Initialization

    421
  • 24.5 SAM-BA Monitor

    422
    • 24.5.1 UART0 Serial Port

      423
    • 24.5.2 Xmodem Protocol

      423
    • 24.5.3 USB Device Port

      423
      • 24.5.3.1 Enumeration Process

        424
      • 24.5.3.2 Communication Endpoints

        424
    • 24.5.4 In Application Programming (IAP) Feature

      425
• 25. Bus Matrix (MATRIX)

  426
  • 25.1 Description

    426
  • 25.2 Master/Slave Management

    426
    • 25.2.1 Matrix Masters

      426
    • 25.2.2 Matrix Slaves

      426
    • 25.2.3 Master to Slave Access

      427
  • 25.3 Memory Mapping

    427
  • 25.4 Special Bus Granting Techniques

    427
    • 25.4.1 No Default Master

      427
    • 25.4.2 Last Access Master

      427
    • 25.4.3 Fixed Default Master

      427
  • 25.5 Arbitration

    428
    • 25.5.1 Arbitration Rules

      428
      • 25.5.1.1 Undefined Length Burst Arbitration

        428
      • 25.5.1.2 Slot Cycle Limit Arbitration

        428
    • 25.5.2 Round-Robin Arbitration

      429
      • 25.5.2.1 Round-Robin arbitration without default master

        429
      • 25.5.2.2 Round-Robin arbitration with last access master

        429
      • 25.5.2.3 Round-Robin arbitration with fixed default master

        429
    • 25.5.3 Fixed Priority Arbitration

      429
  • 25.6 System I/O Configuration

    429
  • 25.7 Register Write Protection

    430
  • 25.8 Bus Matrix (MATRIX) (MATRIX) User Interface

    431
    • 25.8.1 Bus Matrix Master Configuration Registers

      432
    • 25.8.2 Bus Matrix Slave Configuration Registers

      433
    • 25.8.3 Bus Matrix Priority Registers For Slaves

      434
    • 25.8.4 System I/O Configuration Register

      435
    • 25.8.5 SMC NAND Flash Chip Select Configuration Register

      435
    • 25.8.6 Write Protection Mode Register

      437
    • 25.8.7 Write Protection Status Register

      438
• 26. Static Memory Controller (SMC)

  439
  • 26.1 Description

    439
  • 26.2 Embedded Characteristics

    439
  • 26.3 I/O Lines Description

    440
  • 26.4 Product Dependencies

    440
    • 26.4.1 I/O Lines

      440
    • 26.4.2 Power Management

      440
  • 26.5 External Memory Mapping

    440
  • 26.6 Connection to External Devices

    441
    • 26.6.1 Data Bus Width

      441
      • 26.6.1.1 NAND Flash Support

        441
  • 26.7 Application Example

    443
    • 26.7.1 Implementation Examples

      443
      • 26.7.1.1 8-bit NAND Flash

        444
      • 26.7.1.2 NOR Flash

        445
  • 26.8 Standard Read and Write Protocols

    445
    • 26.8.1 Read Waveforms

      445
      • 26.8.1.1 NRD Waveform

        446
      • 26.8.1.2 NCS Waveform

        446
      • 26.8.1.3 Read Cycle

        446
      • 26.8.1.4 Null Delay Setup and Hold

        447
      • 26.8.1.5 Null Pulse

        447
    • 26.8.2 Read Mode

      447
      • 26.8.2.1 Read is Controlled by NRD (READ_MODE = 1):

        447
      • 26.8.2.2 Read is Controlled by NCS (READ_MODE = 0)

        448
    • 26.8.3 Write Waveforms

      449
      • 26.8.3.1 NWE Waveforms

        449
      • 26.8.3.2 NCS Waveforms

        449
      • 26.8.3.3 Write Cycle

        449
      • 26.8.3.4 Null Delay Setup and Hold

        450
      • 26.8.3.5 Null Pulse

        450
    • 26.8.4 Write Mode

      450
      • 26.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1):

        450
      • 26.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0)

        451
    • 26.8.5 Write Protected Registers

      451
    • 26.8.6 Coding Timing Parameters

      452
    • 26.8.7 Reset Values of Timing Parameters

      452
    • 26.8.8 Usage Restriction

      452
  • 26.9 Scrambling/Unscrambling Function

    453
  • 26.10 Automatic Wait States

    453
    • 26.10.1 Chip Select Wait States

      453
    • 26.10.2 Early Read Wait State

      454
    • 26.10.3 Reload User Configuration Wait State

      456
      • 26.10.3.1 User Procedure

        456
      • 26.10.3.2 Slow Clock Mode Transition

        457
    • 26.10.4 Read to Write Wait State

      457
  • 26.11 Data Float Wait States

    457
    • 26.11.1 READ_MODE

      457
    • 26.11.2 TDF Optimization Enabled (TDF_MODE = 1)

      458
    • 26.11.3 TDF Optimization Disabled (TDF_MODE = 0)

      459
  • 26.12 External Wait

    461
    • 26.12.1 Restriction

      461
    • 26.12.2 Frozen Mode

      462
    • 26.12.3 Ready Mode

      464
    • 26.12.4 NWAIT Latency and Read/Write Timings

      466
  • 26.13 Slow Clock Mode

    467
    • 26.13.1 Slow Clock Mode Waveforms

      467
    • 26.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode

      468
  • 26.14 Asynchronous Page Mode

    469
    • 26.14.1 Protocol and Timings in Page Mode

      469
    • 26.14.2 Page Mode Restriction

      470
    • 26.14.3 Sequential and Non-sequential Accesses

      470
  • 26.15 Static Memory Controller (SMC) User Interface

    472
    • 26.15.1 SMC Setup Register

      473
    • 26.15.2 SMC Pulse Register

      474
    • 26.15.3 SMC Cycle Register

      475
    • 26.15.4 SMC MODE Register

      476
    • 26.15.5 SMC OCMS Mode Register

      478
    • 26.15.6 SMC OCMS Key1 Register

      479
    • 26.15.7 SMC OCMS Key2 Register

      480
    • 26.15.8 SMC Write Protect Mode Register

      481
    • 26.15.9 SMC Write Protect Status Register

      482
• 27. Peripheral DMA Controller (PDC)

  483
  • 27.1 Description

    483
  • 27.2 Embedded Characteristics

    483
  • 27.3 Block Diagram

    484
  • 27.4 Functional Description

    485
    • 27.4.1 Configuration

      485
    • 27.4.2 Memory Pointers

      485
    • 27.4.3 Transfer Counters

      485
    • 27.4.4 Data Transfers

      486
    • 27.4.5 PDC Flags and Peripheral Status Register

      486
      • 27.4.5.1 Receive Transfer End

        486
      • 27.4.5.2 Transmit Transfer End

        486
      • 27.4.5.3 Receive Buffer Full

        486
      • 27.4.5.4 Transmit Buffer Empty

        486
  • 27.5 Peripheral DMA Controller (PDC) User Interface

    487
    • 27.5.1 Receive Pointer Register

      488
    • 27.5.2 Receive Counter Register

      489
    • 27.5.3 Transmit Pointer Register

      490
    • 27.5.4 Transmit Counter Register

      491
    • 27.5.5 Receive Next Pointer Register

      492
    • 27.5.6 Receive Next Counter Register

      493
    • 27.5.7 Transmit Next Pointer Register

      494
    • 27.5.8 Transmit Next Counter Register

      495
    • 27.5.9 Transfer Control Register

      496
    • 27.5.10 Transfer Status Register

      497
• 28. Clock Generator

  498
  • 28.1 Description

    498
  • 28.2 Embedded Characteristics

    498
  • 28.3 Block Diagram

    499
  • 28.4 Slow Clock

    499
    • 28.4.1 Slow Clock RC Oscillator

      499
    • 28.4.2 Slow Clock Crystal Oscillator

      500
  • 28.5 Main Clock

    501
    • 28.5.1 Fast RC Oscillator

      501
    • 28.5.2 Fast RC Oscillator Clock Frequency Adjustment

      502
    • 28.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator

      502
    • 28.5.4 Main Clock Oscillator Selection

      503
    • 28.5.5 Switching Main Clock between the Main RC Oscillator and Fast Crystal Oscillator

      503
    • 28.5.6 Software Sequence to Detect the Presence of Fast Crystal

      503
    • 28.5.7 Main Clock Frequency Counter

      504
  • 28.6 Divider and PLL Block

    505
    • 28.6.1 Divider and Phase Lock Loop Programming

      505
• 29. Power Management Controller (PMC)

  507
  • 29.1 Description

    507
  • 29.2 Embedded Characteristics

    507
  • 29.3 Block Diagram

    508
  • 29.4 Master Clock Controller

    508
  • 29.5 Processor Clock Controller

    509
  • 29.6 SysTick Clock

    509
  • 29.7 USB Clock Controller

    509
  • 29.8 Peripheral Clock Controller

    509
  • 29.9 Free-Running Processor Clock

    510
  • 29.10 Programmable Clock Output Controller

    510
  • 29.11 Fast Startup

    510
  • 29.12 Start-up from Embedded Flash

    511
  • 29.13 Main Clock Failure Detector

    512
  • 29.14 Programming Sequence

    513
  • 29.15 Clock Switching Details

    515
    • 29.15.1 Master Clock Switching Timings

      515
    • 29.15.2 Clock Switching Waveforms

      516
  • 29.16 Register Write Protection

    519
  • 29.17 Power Management Controller (PMC) User Interface

    520
    • 29.17.1 PMC System Clock Enable Register

      522
    • 29.17.2 PMC System Clock Disable Register

      523
    • 29.17.3 PMC System Clock Status Register

      524
    • 29.17.4 PMC Peripheral Clock Enable Register 0

      525
    • 29.17.5 PMC Peripheral Clock Disable Register 0

      526
    • 29.17.6 PMC Peripheral Clock Status Register 0

      527
    • 29.17.7 PMC Clock Generator Main Oscillator Register

      528
    • 29.17.8 PMC Clock Generator Main Clock Frequency Register

      530
    • 29.17.9 PMC Clock Generator PLLA Register

      531
    • 29.17.10 PMC Clock Generator PLLB Register

      532
    • 29.17.11 PMC Master Clock Register

      533
    • 29.17.12 PMC USB Clock Register

      535
    • 29.17.13 PMC Programmable Clock Register

      536
    • 29.17.14 PMC Interrupt Enable Register

      537
    • 29.17.15 PMC Interrupt Disable Register

      538
    • 29.17.16 PMC Status Register

      539
    • 29.17.17 PMC Interrupt Mask Register

      541
    • 29.17.18 PMC Fast Start-up Mode Register

      542
    • 29.17.19 PMC Fast Start-up Polarity Register

      543
    • 29.17.20 PMC Fault Output Clear Register

      545
    • 29.17.21 PMC Write Protection Mode Register

      546
    • 29.17.22 PMC Write Protection Status Register

      547
    • 29.17.23 PMC Peripheral Clock Enable Register 1

      548
    • 29.17.24 PMC Peripheral Clock Disable Register 1

      549
    • 29.17.25 PMC Peripheral Clock Status Register 1

      550
    • 29.17.26 PMC Oscillator Calibration Register

      551
• 30. Chip Identifier (CHIPID)

  552
  • 30.1 Description

    552
  • 30.2 Embedded Characteristics

    552
  • 30.3 Chip Identifier (CHIPID) User Interface

    553
    • 30.3.1 Chip ID Register

      554
    • 30.3.2 Chip ID Extension Register

      557
• 31. Parallel Input/Output Controller (PIO)

  558
  • 31.1 Description

    558
  • 31.2 Embedded Characteristics

    558
  • 31.3 Block Diagram

    559
  • 31.4 Product Dependencies

    561
    • 31.4.1 Pin Multiplexing

      561
    • 31.4.2 External Interrupt Lines

      561
    • 31.4.3 Power Management

      561
    • 31.4.4 Interrupt Generation

      561
  • 31.5 Functional Description

    562
    • 31.5.1 Pull-up and Pull-down Resistor Control

      563
    • 31.5.2 I/O Line or Peripheral Function Selection

      563
    • 31.5.3 Peripheral A or B or C or D Selection

      563
    • 31.5.4 Output Control

      564
    • 31.5.5 Synchronous Data Output

      564
    • 31.5.6 Multi-Drive Control (Open Drain)

      564
    • 31.5.7 Output Line Timings

      564
    • 31.5.8 Inputs

      565
    • 31.5.9 Input Glitch and Debouncing Filters

      565
    • 31.5.10 Input Edge/Level Interrupt

      566
      • 31.5.10.1 Example

        567
      • 31.5.10.2 Interrupt Mode Configuration

        568
      • 31.5.10.3 Edge or Level Detection Configuration

        568
      • 31.5.10.4 Falling/Rising Edge or Low/High-Level Detection Configuration

        568
    • 31.5.11 I/O Lines Lock

      568
    • 31.5.12 Programmable Schmitt Trigger

      568
    • 31.5.13 Parallel Capture Mode

      569
      • 31.5.13.1 Overview

        569
      • 31.5.13.2 Functional Description

        569
      • 31.5.13.3 Restrictions

        571
      • 31.5.13.4 Programming Sequence

        571
    • 31.5.14 Register Write Protection

      573
  • 31.6 I/O Lines Programming Example

    574
  • 31.7 Parallel Input/Output Controller (PIO) User Interface

    575
    • 31.7.1 PIO Enable Register

      578
    • 31.7.2 PIO Disable Register

      578
    • 31.7.3 PIO Status Register

      579
    • 31.7.4 PIO Output Enable Register

      580
    • 31.7.5 PIO Output Disable Register

      580
    • 31.7.6 PIO Output Status Register

      581
    • 31.7.7 PIO Input Filter Enable Register

      582
    • 31.7.8 PIO Input Filter Disable Register

      582
    • 31.7.9 PIO Input Filter Status Register

      583
    • 31.7.10 PIO Set Output Data Register

      584
    • 31.7.11 PIO Clear Output Data Register

      584
    • 31.7.12 PIO Output Data Status Register

      585
    • 31.7.13 PIO Pin Data Status Register

      586
    • 31.7.14 PIO Interrupt Enable Register

      587
    • 31.7.15 PIO Interrupt Disable Register

      587
    • 31.7.16 PIO Interrupt Mask Register

      588
    • 31.7.17 PIO Interrupt Status Register

      589
    • 31.7.18 PIO Multi-driver Enable Register

      590
    • 31.7.19 PIO Multi-driver Disable Register

      590
    • 31.7.20 PIO Multi-driver Status Register

      591
    • 31.7.21 PIO Pull-Up Disable Register

      592
    • 31.7.22 PIO Pull-Up Enable Register

      592
    • 31.7.23 PIO Pull-Up Status Register

      593
    • 31.7.24 PIO Peripheral ABCD Select Register 1

      594
    • 31.7.25 PIO Peripheral ABCD Select Register 2

      595
    • 31.7.26 PIO Input Filter Slow Clock Disable Register

      596
    • 31.7.27 PIO Input Filter Slow Clock Enable Register

      596
    • 31.7.28 PIO Input Filter Slow Clock Status Register

      597
    • 31.7.29 PIO Slow Clock Divider Debouncing Register

      598
    • 31.7.30 PIO Pad Pull-Down Disable Register

      599
    • 31.7.31 PIO Pad Pull-Down Enable Register

      599
    • 31.7.32 PIO Pad Pull-Down Status Register

      600
    • 31.7.33 PIO Output Write Enable Register

      601
    • 31.7.34 PIO Output Write Disable Register

      601
    • 31.7.35 PIO Output Write Status Register

      602
    • 31.7.36 PIO Additional Interrupt Modes Enable Register

      603
    • 31.7.37 PIO Additional Interrupt Modes Disable Register

      603
    • 31.7.38 PIO Additional Interrupt Modes Mask Register

      604
    • 31.7.39 PIO Edge Select Register

      605
    • 31.7.40 PIO Level Select Register

      605
    • 31.7.41 PIO Edge/Level Status Register

      606
    • 31.7.42 PIO Falling Edge/Low-Level Select Register

      606
    • 31.7.43 PIO Rising Edge/High-Level Select Register

      607
    • 31.7.44 PIO Fall/Rise - Low/High Status Register

      607
    • 31.7.45 PIO Lock Status Register

      608
    • 31.7.46 PIO Write Protection Mode Register

      609
    • 31.7.47 PIO Write Protection Status Register

      610
    • 31.7.48 PIO Schmitt Trigger Register

      611
    • 31.7.49 PIO Parallel Capture Mode Register

      612
    • 31.7.50 PIO Parallel Capture Interrupt Enable Register

      613
    • 31.7.51 PIO Parallel Capture Interrupt Disable Register

      614
    • 31.7.52 PIO Parallel Capture Interrupt Mask Register

      615
    • 31.7.53 PIO Parallel Capture Interrupt Status Register

      616
    • 31.7.54 PIO Parallel Capture Reception Holding Register

      617
• 32. Synchronous Serial Controller (SSC)

  618
  • 32.1 Description

    618
  • 32.2 Embedded Characteristics

    618
  • 32.3 Block Diagram

    619
  • 32.4 Application Block Diagram

    619
  • 32.5 Pin Name List

    620
  • 32.6 Product Dependencies

    620
    • 32.6.1 I/O Lines

      620
    • 32.6.2 Power Management

      620
    • 32.6.3 Interrupt

      620
  • 32.7 Functional Description

    621
    • 32.7.1 Clock Management

      621
      • 32.7.1.1 Clock Divider

        622
      • 32.7.1.2 Transmitter Clock Management

        623
      • 32.7.1.3 Receiver Clock Management

        623
      • 32.7.1.4 Serial Clock Ratio Considerations

        624
    • 32.7.2 Transmitter Operations

      624
    • 32.7.3 Receiver Operations

      625
    • 32.7.4 Start

      626
    • 32.7.5 Frame Sync

      628
      • 32.7.5.1 Frame Sync Data

        628
      • 32.7.5.2 Frame Sync Edge Detection

        628
    • 32.7.6 Receive Compare Modes

      628
      • 32.7.6.1 Compare Functions

        628
    • 32.7.7 Data Format

      629
    • 32.7.8 Loop Mode

      631
    • 32.7.9 Interrupt

      631
  • 32.8 SSC Application Examples

    632
    • 32.8.1 Write Protection Registers

      634
  • 32.9 Synchronous Serial Controller (SSC) User Interface

    635
    • 32.9.1 SSC Control Register

      636
    • 32.9.2 SSC Clock Mode Register

      637
    • 32.9.3 SSC Receive Clock Mode Register

      638
    • 32.9.4 SSC Receive Frame Mode Register

      640
    • 32.9.5 SSC Transmit Clock Mode Register

      642
    • 32.9.6 SSC Transmit Frame Mode Register

      644
    • 32.9.7 SSC Receive Holding Register

      646
    • 32.9.8 SSC Transmit Holding Register

      647
    • 32.9.9 SSC Receive Synchronization Holding Register

      648
    • 32.9.10 SSC Transmit Synchronization Holding Register

      649
    • 32.9.11 SSC Receive Compare 0 Register

      650
    • 32.9.12 SSC Receive Compare 1 Register

      651
    • 32.9.13 SSC Status Register

      652
    • 32.9.14 SSC Interrupt Enable Register

      654
    • 32.9.15 SSC Interrupt Disable Register

      656
    • 32.9.16 SSC Interrupt Mask Register

      658
    • 32.9.17 SSC Write Protect Mode Register

      660
    • 32.9.18 SSC Write Protect Status Register

      661
• 33. Serial Peripheral Interface (SPI)

  662
  • 33.1 Description

    662
  • 33.2 Embedded Characteristics

    663
  • 33.3 Block Diagram

    664
  • 33.4 Application Block Diagram

    665
  • 33.5 Signal Description

    665
  • 33.6 Product Dependencies

    665
    • 33.6.1 I/O Lines

      665
    • 33.6.2 Power Management

      666
    • 33.6.3 Interrupt

      666
    • 33.6.4 Peripheral DMA Controller (PDC)

      666
  • 33.7 Functional Description

    666
    • 33.7.1 Modes of Operation

      666
    • 33.7.2 Data Transfer

      667
    • 33.7.3 Master Mode Operations

      668
      • 33.7.3.1 Master Mode Block Diagram

        669
      • 33.7.3.2 Master Mode Flow Diagram

        670
      • 33.7.3.3 Clock Generation

        672
      • 33.7.3.4 Transfer Delays

        672
      • 33.7.3.5 Peripheral Selection

        673
      • 33.7.3.6 SPI Peripheral DMA Controller (PDC)

        673
        • Transfer Size

          674
      • 33.7.3.7 Peripheral Chip Select Decoding

        674
      • 33.7.3.8 Peripheral Deselection without PDC

        675
      • 33.7.3.9 Peripheral Deselection with PDC

        675
      • 33.7.3.10 Mode Fault Detection

        676
    • 33.7.4 SPI Slave Mode

      677
    • 33.7.5 Register Write Protection

      679
  • 33.8 Serial Peripheral Interface (SPI) User Interface

    680
    • 33.8.1 SPI Control Register

      681
    • 33.8.2 SPI Mode Register

      682
    • 33.8.3 SPI Receive Data Register

      684
    • 33.8.4 SPI Transmit Data Register

      685
    • 33.8.5 SPI Status Register

      686
    • 33.8.6 SPI Interrupt Enable Register

      688
    • 33.8.7 SPI Interrupt Disable Register

      689
    • 33.8.8 SPI Interrupt Mask Register

      690
    • 33.8.9 SPI Chip Select Register

      691
    • 33.8.10 SPI Write Protection Mode Register

      694
    • 33.8.11 SPI Write Protection Status Register

      695
• 34. Two-wire Interface (TWI)

  696
  • 34.1 Description

    696
  • 34.2 Embedded Characteristics

    696
  • 34.3 List of Abbreviations

    697
  • 34.4 Block Diagram

    697
  • 34.5 Application Block Diagram

    698
    • 34.5.1 I/O Lines Description

      698
  • 34.6 Product Dependencies

    698
    • 34.6.1 I/O Lines

      698
    • 34.6.2 Power Management

      698
    • 34.6.3 Interrupt

      699
  • 34.7 Functional Description

    700
    • 34.7.1 Transfer Format

      700
    • 34.7.2 Modes of Operation

      700
  • 34.8 Master Mode

    701
    • 34.8.1 Definition

      701
    • 34.8.2 Application Block Diagram

      701
    • 34.8.3 Programming Master Mode

      701
    • 34.8.4 Master Transmitter Mode

      701
    • 34.8.5 Master Receiver Mode

      703
    • 34.8.6 Internal Address

      704
      • 34.8.6.1 7-bit Slave Addressing

        704
      • 34.8.6.2 10-bit Slave Addressing

        705
    • 34.8.7 Using the Peripheral DMA Controller (PDC)

      705
      • 34.8.7.1 Data Transmit with the PDC

        705
      • 34.8.7.2 Data Receive with the PDC

        706
    • 34.8.8 SMBUS Quick Command (Master Mode Only)

      706
    • 34.8.9 Read-write Flowcharts

      707
  • 34.9 Multi-master Mode

    713
    • 34.9.1 Definition

      713
    • 34.9.2 Different Multi-master Modes

      713
      • 34.9.2.1 TWI as Master Only

        713
      • 34.9.2.2 TWI as Master or Slave

        713
  • 34.10 Slave Mode

    716
    • 34.10.1 Definition

      716
    • 34.10.2 Application Block Diagram

      716
    • 34.10.3 Programming Slave Mode

      716
    • 34.10.4 Receiving Data

      716
      • 34.10.4.1 Read Sequence

        716
      • 34.10.4.2 Write Sequence

        717
      • 34.10.4.3 Clock Synchronization Sequence

        717
      • 34.10.4.4 General Call

        717
    • 34.10.5 Data Transfer

      717
      • 34.10.5.1 Read Operation

        717
      • 34.10.5.2 Write Operation

        718
      • 34.10.5.3 General Call

        718
      • 34.10.5.4 Clock Synchronization

        719
      • 34.10.5.5 Reversal after a Repeated Start

        720
    • 34.10.6 Using the Peripheral DMA Controller (PDC) in Slave Mode

      721
      • 34.10.6.1 Data Transmit with the PDC in Slave Mode

        721
      • 34.10.6.2 Data Receive with the PDC in Slave Mode

        721
    • 34.10.7 Read Write Flowcharts

      722
  • 34.11 Two-wire Interface (TWI) User Interface

    723
    • 34.11.1 TWI Control Register

      724
    • 34.11.2 TWI Master Mode Register

      726
    • 34.11.3 TWI Slave Mode Register

      727
    • 34.11.4 TWI Internal Address Register

      728
    • 34.11.5 TWI Clock Waveform Generator Register

      729
    • 34.11.6 TWI Status Register

      730
    • 34.11.7 TWI Interrupt Enable Register

      733
    • 34.11.8 TWI Interrupt Disable Register

      734
    • 34.11.9 TWI Interrupt Mask Register

      735
    • 34.11.10 TWI Receive Holding Register

      736
    • 34.11.11 TWI Transmit Holding Register

      737
• 35. Universal Asynchronous Receiver Transmitter (UART)

  738
  • 35.1 Description

    738
  • 35.2 Embedded Characteristics

    738
  • 35.3 Block Diagram

    738
  • 35.4 Product Dependencies

    739
    • 35.4.1 I/O Lines

      739
    • 35.4.2 Power Management

      739
    • 35.4.3 Interrupt Source

      739
  • 35.5 UART Operations

    739
    • 35.5.1 Baud Rate Generator

      739
    • 35.5.2 Receiver

      740
      • 35.5.2.1 Receiver Reset, Enable and Disable

        740
      • 35.5.2.2 Start Detection and Data Sampling

        740
      • 35.5.2.3 Receiver Ready

        741
      • 35.5.2.4 Receiver Overrun

        741
      • 35.5.2.5 Parity Error

        741
      • 35.5.2.6 Receiver Framing Error

        742
    • 35.5.3 Transmitter

      742
      • 35.5.3.1 Transmitter Reset, Enable and Disable

        742
      • 35.5.3.2 Transmit Format

        742
      • 35.5.3.3 Transmitter Control

        743
    • 35.5.4 Peripheral DMA Controller (PDC)

      743
    • 35.5.5 Test Modes

      743
  • 35.6 Universal Asynchronous Receiver Transmitter (UART) User Interface

    745
    • 35.6.1 UART Control Register

      746
    • 35.6.2 UART Mode Register

      747
    • 35.6.3 UART Interrupt Enable Register

      748
    • 35.6.4 UART Interrupt Disable Register

      749
    • 35.6.5 UART Interrupt Mask Register

      750
    • 35.6.6 UART Status Register

      751
    • 35.6.7 UART Receiver Holding Register

      753
    • 35.6.8 UART Transmit Holding Register

      754
    • 35.6.9 UART Baud Rate Generator Register

      755
• 36. Universal Synchronous Asynchronous Receiver Transceiver (USART)

  756
  • 36.1 Description

    756
  • 36.2 Embedded Characteristics

    756
  • 36.3 Block Diagram

    757
  • 36.4 Application Block Diagram

    758
  • 36.5 I/O Lines Description

    759
  • 36.6 Product Dependencies

    760
    • 36.6.1 I/O Lines

      760
    • 36.6.2 Power Management

      760
    • 36.6.3 Interrupt

      760
  • 36.7 Functional Description

    761
    • 36.7.1 Baud Rate Generator

      761
      • 36.7.1.1 Baud Rate in Asynchronous Mode

        761
      • 36.7.1.2 Fractional Baud Rate in Asynchronous Mode

        762
      • 36.7.1.3 Baud Rate in Synchronous Mode or SPI Mode

        763
      • 36.7.1.4 Baud Rate in ISO 7816 Mode

        763
    • 36.7.2 Receiver and Transmitter Control

      765
    • 36.7.3 Synchronous and Asynchronous Modes

      765
      • 36.7.3.1 Transmitter Operations

        765
      • 36.7.3.2 Manchester Encoder

        766
      • 36.7.3.3 Asynchronous Receiver

        768
      • 36.7.3.4 Manchester Decoder

        769
      • 36.7.3.5 Radio Interface: Manchester Encoded USART Application

        771
      • 36.7.3.6 Synchronous Receiver

        772
      • 36.7.3.7 Receiver Operations

        773
      • 36.7.3.8 Parity

        773
      • 36.7.3.9 Multidrop Mode

        774
      • 36.7.3.10 Transmitter Timeguard

        774
      • 36.7.3.11 Receiver Time-out

        775
      • 36.7.3.12 Framing Error

        777
      • 36.7.3.13 Transmit Break

        777
      • 36.7.3.14 Receive Break

        778
      • 36.7.3.15 Hardware Handshaking

        778
    • 36.7.4 ISO7816 Mode

      779
      • 36.7.4.1 ISO7816 Mode Overview

        779
      • 36.7.4.2 Protocol T = 0

        780
      • 36.7.4.3 Protocol T = 1

        781
    • 36.7.5 IrDA Mode

      781
      • 36.7.5.1 IrDA Modulation

        782
      • 36.7.5.2 IrDA Baud Rate

        782
      • 36.7.5.3 IrDA Demodulator

        783
    • 36.7.6 RS485 Mode

      783
    • 36.7.7 Modem Mode

      785
    • 36.7.8 SPI Mode

      786
      • 36.7.8.1 Modes of Operation

        786
      • 36.7.8.2 Baud Rate

        786
      • 36.7.8.3 Data Transfer

        787
      • 36.7.8.4 Receiver and Transmitter Control

        788
      • 36.7.8.5 Character Transmission

        788
      • 36.7.8.6 Character Reception

        789
      • 36.7.8.7 Receiver Timeout

        789
    • 36.7.9 Test Modes

      789
      • 36.7.9.1 Normal Mode

        789
      • 36.7.9.2 Automatic Echo Mode

        790
      • 36.7.9.3 Local Loopback Mode

        790
      • 36.7.9.4 Remote Loopback Mode

        790
    • 36.7.10 Register Write Protection

      791
  • 36.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface

    792
    • 36.8.1 USART Control Register

      793
    • 36.8.2 USART Control Register (SPI_MODE)

      796
    • 36.8.3 USART Mode Register

      798
    • 36.8.4 USART Mode Register (SPI_MODE)

      802
    • 36.8.5 USART Interrupt Enable Register

      804
    • 36.8.6 USART Interrupt Enable Register (SPI_MODE)

      806
    • 36.8.7 USART Interrupt Disable Register

      807
    • 36.8.8 USART Interrupt Disable Register (SPI_MODE)

      809
    • 36.8.9 USART Interrupt Mask Register

      810
    • 36.8.10 USART Interrupt Mask Register (SPI_MODE)

      812
    • 36.8.11 USART Channel Status Register

      813
    • 36.8.12 USART Channel Status Register (SPI_MODE)

      816
    • 36.8.13 USART Receive Holding Register

      817
    • 36.8.14 USART Transmit Holding Register

      818
    • 36.8.15 USART Baud Rate Generator Register

      819
    • 36.8.16 USART Receiver Time-out Register

      820
    • 36.8.17 USART Transmitter Timeguard Register

      821
    • 36.8.18 USART FI DI RATIO Register

      822
    • 36.8.19 USART Number of Errors Register

      823
    • 36.8.20 USART IrDA FILTER Register

      824
    • 36.8.21 USART Manchester Configuration Register

      825
    • 36.8.22 USART Write Protection Mode Register

      827
    • 36.8.23 USART Write Protection Status Register

      828
• 37. Timer Counter (TC)

  829
  • 37.1 Description

    829
  • 37.2 Embedded Characteristics

    829
  • 37.3 Block Diagram

    830
  • 37.4 Pin Name List

    831
  • 37.5 Product Dependencies

    831
    • 37.5.1 I/O Lines

      831
    • 37.5.2 Power Management

      832
    • 37.5.3 Interrupt

      832
    • 37.5.4 Fault Output

      832
  • 37.6 Functional Description

    832
    • 37.6.1 TC Description

      832
    • 37.6.2 16-bit Counter

      832
    • 37.6.3 Clock Selection

      832
    • 37.6.4 Clock Control

      834
    • 37.6.5 TC Operating Modes

      834
    • 37.6.6 Trigger

      834
    • 37.6.7 Capture Operating Mode

      835
    • 37.6.8 Capture Registers A and B

      835
    • 37.6.9 Trigger Conditions

      835
    • 37.6.10 Waveform Operating Mode

      837
    • 37.6.11 Waveform Selection

      837
      • 37.6.11.1 WAVSEL = 00

        839
      • 37.6.11.2 WAVSEL = 10

        840
      • 37.6.11.3 WAVSEL = 01

        841
      • 37.6.11.4 WAVSEL = 11

        842
    • 37.6.12 External Event/Trigger Conditions

      843
    • 37.6.13 Output Controller

      843
    • 37.6.14 Quadrature Decoder Logic

      843
      • 37.6.14.1 Description

        843
      • 37.6.14.2 Input Pre-processing

        844
      • 37.6.14.3 Direction Status and Change Detection

        847
      • 37.6.14.4 Position and Rotation Measurement

        848
      • 37.6.14.5 Speed Measurement

        849
    • 37.6.15 2-bit Gray Up/Down Counter for Stepper Motor

      849
    • 37.6.16 Register Write Protection

      849
    • 37.6.17 Fault Mode

      850
  • 37.7 Timer Counter (TC) User Interface

    851
    • 37.7.1 TC Channel Control Register

      852
    • 37.7.2 TC Channel Mode Register: Capture Mode

      853
    • 37.7.3 TC Channel Mode Register: Waveform Mode

      855
    • 37.7.4 TC Stepper Motor Mode Register

      859
    • 37.7.5 TC Counter Value Register

      860
    • 37.7.6 TC Register A

      861
    • 37.7.7 TC Register B

      862
    • 37.7.8 TC Register C

      863
    • 37.7.9 TC Status Register

      864
    • 37.7.10 TC Interrupt Enable Register

      866
    • 37.7.11 TC Interrupt Disable Register

      868
    • 37.7.12 TC Interrupt Mask Register

      870
    • 37.7.13 TC Block Control Register

      872
    • 37.7.14 TC Block Mode Register

      873
    • 37.7.15 TC QDEC Interrupt Enable Register

      876
    • 37.7.16 TC QDEC Interrupt Disable Register

      877
    • 37.7.17 TC QDEC Interrupt Mask Register

      878
    • 37.7.18 TC QDEC Interrupt Status Register

      879
    • 37.7.19 TC Fault Mode Register

      880
    • 37.7.20 TC Write Protection Mode Register

      881
• 38. High Speed MultiMedia Card Interface (HSMCI)

  882
  • 38.1 Description

    882
  • 38.2 Embedded Characteristics

    882
  • 38.3 Block Diagram

    883
  • 38.4 Application Block Diagram

    884
  • 38.5 Pin Name List

    884
  • 38.6 Product Dependencies

    885
    • 38.6.1 I/O Lines

      885
    • 38.6.2 Power Management

      885
    • 38.6.3 Interrupt

      885
  • 38.7 Bus Topology

    885
  • 38.8 High Speed MultiMedia Card Operations

    888
    • 38.8.1 Command - Response Operation

      888
    • 38.8.2 Data Transfer Operation

      891
    • 38.8.3 Read Operation

      891
    • 38.8.4 Write Operation

      893
  • 38.9 SD/SDIO Card Operation

    896
    • 38.9.1 SDIO Data Transfer Type

      896
    • 38.9.2 SDIO Interrupts

      896
  • 38.10 CE-ATA Operation

    897
    • 38.10.1 Executing an ATA Polling Command

      897
    • 38.10.2 Executing an ATA Interrupt Command

      897
    • 38.10.3 Aborting an ATA Command

      897
    • 38.10.4 CE-ATA Error Recovery

      897
  • 38.11 HSMCI Boot Operation Mode

    898
    • 38.11.1 Boot Procedure, Processor Mode

      898
  • 38.12 HSMCI Transfer Done Timings

    898
    • 38.12.1 Definition

      898
    • 38.12.2 Read Access

      898
    • 38.12.3 Write Access

      899
  • 38.13 Register Write Protection

    900
  • 38.14 High Speed MultiMedia Card Interface (HSMCI) User Interface

    901
    • 38.14.1 HSMCI Control Register

      902
    • 38.14.2 HSMCI Mode Register

      903
    • 38.14.3 HSMCI Data Timeout Register

      905
    • 38.14.4 HSMCI SDCard/SDIO Register

      906
    • 38.14.5 HSMCI Argument Register

      907
    • 38.14.6 HSMCI Command Register

      908
    • 38.14.7 HSMCI Block Register

      910
    • 38.14.8 HSMCI Completion Signal Timeout Register

      911
    • 38.14.9 HSMCI Response Register

      912
    • 38.14.10 HSMCI Receive Data Register

      913
    • 38.14.11 HSMCI Transmit Data Register

      914
    • 38.14.12 HSMCI Status Register

      915
    • 38.14.13 HSMCI Interrupt Enable Register

      919
    • 38.14.14 HSMCI Interrupt Disable Register

      921
    • 38.14.15 HSMCI Interrupt Mask Register

      923
    • 38.14.16 HSMCI Configuration Register

      925
    • 38.14.17 HSMCI Write Protection Mode Register

      926
    • 38.14.18 HSMCI Write Protection Status Register

      927
• 39. Pulse Width Modulation Controller (PWM)

  928
  • 39.1 Description

    928
  • 39.2 Embedded Characteristics

    928
  • 39.3 Block Diagram

    929
  • 39.4 I/O Lines Description

    930
  • 39.5 Product Dependencies

    931
    • 39.5.1 I/O Lines

      931
    • 39.5.2 Power Management

      932
    • 39.5.3 Interrupt Sources

      932
    • 39.5.4 Fault Inputs

      932
  • 39.6 Functional Description

    933
    • 39.6.1 PWM Clock Generator

      933
    • 39.6.2 PWM Channel

      934
      • 39.6.2.1 Channel Block Diagram

        934
      • 39.6.2.2 Comparator

        935
      • 39.6.2.3 2-bit Gray Up/Down Counter for Stepper Motor

        937
      • 39.6.2.4 Dead-Time Generator

        938
      • 39.6.2.5 Output Override

        939
      • 39.6.2.6 Fault Protection

        940
      • 39.6.2.7 Synchronous Channels

        941
    • 39.6.3 PWM Comparison Units

      946
    • 39.6.4 PWM Event Lines

      948
    • 39.6.5 PWM Controller Operations

      949
      • 39.6.5.1 Initialization

        949
      • 39.6.5.2 Source Clock Selection Criteria

        949
      • 39.6.5.3 Changing the Duty-Cycle, the Period and the Dead-Times

        949
      • 39.6.5.4 Changing the Synchronous Channels Update Period

        950
      • 39.6.5.5 Changing the Comparison Value and the Comparison Configuration

        951
      • 39.6.5.6 Interrupts

        952
      • 39.6.5.7 Register Write Protection

        952
  • 39.7 Pulse Width Modulation Controller (PWM) User Interface

    954
    • 39.7.1 PWM Clock Register

      957
    • 39.7.2 PWM Enable Register

      958
    • 39.7.3 PWM Disable Register

      959
    • 39.7.4 PWM Status Register

      960
    • 39.7.5 PWM Interrupt Enable Register 1

      961
    • 39.7.6 PWM Interrupt Disable Register 1

      962
    • 39.7.7 PWM Interrupt Mask Register 1

      963
    • 39.7.8 PWM Interrupt Status Register 1

      964
    • 39.7.9 PWM Sync Channels Mode Register

      965
    • 39.7.10 PWM Sync Channels Update Control Register

      966
    • 39.7.11 PWM Sync Channels Update Period Register

      967
    • 39.7.12 PWM Sync Channels Update Period Update Register

      968
    • 39.7.13 PWM Interrupt Enable Register 2

      969
    • 39.7.14 PWM Interrupt Disable Register 2

      970
    • 39.7.15 PWM Interrupt Mask Register 2

      971
    • 39.7.16 PWM Interrupt Status Register 2

      972
    • 39.7.17 PWM Output Override Value Register

      973
    • 39.7.18 PWM Output Selection Register

      974
    • 39.7.19 PWM Output Selection Set Register

      975
    • 39.7.20 PWM Output Selection Clear Register

      976
    • 39.7.21 PWM Output Selection Set Update Register

      977
    • 39.7.22 PWM Output Selection Clear Update Register

      978
    • 39.7.23 PWM Fault Mode Register

      979
    • 39.7.24 PWM Fault Status Register

      980
    • 39.7.25 PWM Fault Clear Register

      981
    • 39.7.26 PWM Fault Protection Value Register

      982
    • 39.7.27 PWM Fault Protection Enable Register

      983
    • 39.7.28 PWM Event Line x Register

      984
    • 39.7.29 PWM Stepper Motor Mode Register

      985
    • 39.7.30 PWM Write Protection Control Register

      986
    • 39.7.31 PWM Write Protection Status Register

      988
    • 39.7.32 PWM Comparison x Value Register

      989
    • 39.7.33 PWM Comparison x Value Update Register

      990
    • 39.7.34 PWM Comparison x Mode Register

      991
    • 39.7.35 PWM Comparison x Mode Update Register

      992
    • 39.7.36 PWM Channel Mode Register

      993
    • 39.7.37 PWM Channel Duty Cycle Register

      995
    • 39.7.38 PWM Channel Duty Cycle Update Register

      996
    • 39.7.39 PWM Channel Period Register

      997
    • 39.7.40 PWM Channel Period Update Register

      998
    • 39.7.41 PWM Channel Counter Register

      999
    • 39.7.42 PWM Channel Dead Time Register

      1000
    • 39.7.43 PWM Channel Dead Time Update Register

      1001
• 40. USB Device Port (UDP)

  1002
  • 40.1 Description

    1002
  • 40.2 Embedded Characteristics

    1002
  • 40.3 Block Diagram

    1003
    • 40.3.1 Signal Description

      1003
  • 40.4 Product Dependencies

    1003
    • 40.4.1 I/O Lines

      1004
    • 40.4.2 Power Management

      1004
    • 40.4.3 Interrupt

      1004
  • 40.5 Typical Connection

    1005
    • 40.5.1 USB Device Transceiver

      1005
    • 40.5.2 VBUS Monitoring

      1005
  • 40.6 Functional Description

    1006
    • 40.6.1 USB 2.0 Full-speed Introduction

      1006
      • 40.6.1.1 USB 2.0 Full-speed Transfer Types

        1006
      • 40.6.1.2 USB Bus Transactions

        1006
      • 40.6.1.3 USB Transfer Event Definitions

        1007
    • 40.6.2 Handling Transactions with USB 2.0 Device Peripheral

      1008
      • 40.6.2.1 Setup Transaction

        1008
      • 40.6.2.2 Data IN Transaction

        1008
        • Using Endpoints Without Ping-pong Attributes

          1008
        • Using Endpoints With Ping-pong Attribute

          1009
      • 40.6.2.3 Data OUT Transaction

        1011
        • Data OUT Transaction Without Ping-pong Attributes

          1011
        • Using Endpoints With Ping-pong Attributes

          1012
      • 40.6.2.4 Stall Handshake

        1014
      • 40.6.2.5 Transmit Data Cancellation

        1015
        • Endpoints Without Dual-Banks

          1015
        • Endpoints With Dual-Banks

          1015
    • 40.6.3 Controlling Device States

      1016
      • 40.6.3.1 Not Powered State

        1016
      • 40.6.3.2 Entering Attached State

        1017
      • 40.6.3.3 From Powered State to Default State

        1017
      • 40.6.3.4 From Default State to Address State

        1017
      • 40.6.3.5 From Address State to Configured State

        1017
      • 40.6.3.6 Entering in Suspend State

        1017
      • 40.6.3.7 Receiving a Host Resume

        1018
      • 40.6.3.8 Sending a Device Remote Wakeup

        1018
  • 40.7 USB Device Port (UDP) User Interface

    1019
    • 40.7.1 UDP Frame Number Register

      1020
    • 40.7.2 UDP Global State Register

      1021
    • 40.7.3 UDP Function Address Register

      1022
    • 40.7.4 UDP Interrupt Enable Register

      1023
    • 40.7.5 UDP Interrupt Disable Register

      1025
    • 40.7.6 UDP Interrupt Mask Register

      1027
    • 40.7.7 UDP Interrupt Status Register

      1029
    • 40.7.8 UDP Interrupt Clear Register

      1031
    • 40.7.9 UDP Reset Endpoint Register

      1032
    • 40.7.10 UDP Endpoint Control and Status Register (CONTROL_BULK)

      1033
    • 40.7.11 UDP Endpoint Control and Status Register (ISOCHRONOUS)

      1038
    • 40.7.12 UDP FIFO Data Register

      1042
    • 40.7.13 UDP Transceiver Control Register

      1043
• 41. Analog Comparator Controller (ACC)

  1044
  • 41.1 Description

    1044
  • 41.2 Embedded Characteristics

    1044
  • 41.3 Block Diagram

    1045
  • 41.4 Pin Name List

    1045
  • 41.5 Product Dependencies

    1046
    • 41.5.1 I/O Lines

      1046
    • 41.5.2 Power Management

      1046
    • 41.5.3 Interrupt

      1046
    • 41.5.4 Fault Output

      1046
  • 41.6 Functional Description

    1047
    • 41.6.1 Description

      1047
    • 41.6.2 Analog Settings

      1047
    • 41.6.3 Output Masking Period

      1047
    • 41.6.4 Fault Mode

      1047
    • 41.6.5 Register Write Protection

      1047
  • 41.7 Analog Comparator Controller (ACC) User Interface

    1048
    • 41.7.1 ACC Control Register

      1049
    • 41.7.2 ACC Mode Register

      1050
    • 41.7.3 ACC Interrupt Enable Register

      1052
    • 41.7.4 ACC Interrupt Disable Register

      1053
    • 41.7.5 ACC Interrupt Mask Register

      1054
    • 41.7.6 ACC Interrupt Status Register

      1055
    • 41.7.7 ACC Analog Control Register

      1056
    • 41.7.8 ACC Write Protection Mode Register

      1057
    • 41.7.9 ACC Write Protection Status Register

      1058
• 42. Analog-to-Digital Converter (ADC)

  1059
  • 42.1 Description

    1059
  • 42.2 Embedded Characteristics

    1060
  • 42.3 Block Diagram

    1061
  • 42.4 Signal Description

    1062
  • 42.5 Product Dependencies

    1063
    • 42.5.1 Power Management

      1063
    • 42.5.2 Interrupt Sources

      1063
    • 42.5.3 Analog Inputs

      1063
    • 42.5.4 Temperature Sensor

      1063
    • 42.5.5 I/O Lines

      1063
    • 42.5.6 Timer Triggers

      1064
    • 42.5.7 PWM Event Line

      1064
    • 42.5.8 Fault Output

      1064
    • 42.5.9 Conversion Performances

      1064
  • 42.6 Functional Description

    1064
    • 42.6.1 Analog-to-Digital Conversion

      1064
    • 42.6.2 Conversion Reference

      1066
    • 42.6.3 Conversion Resolution

      1066
    • 42.6.4 Conversion Results

      1066
    • 42.6.5 Conversion Triggers

      1068
    • 42.6.6 Sleep Mode and Conversion Sequencer

      1068
    • 42.6.7 Comparison Window

      1069
    • 42.6.8 Differential Inputs

      1069
    • 42.6.9 Input Gain and Offset

      1070
    • 42.6.10 ADC Timings

      1072
    • 42.6.11 Automatic Calibration

      1073
    • 42.6.12 Buffer Structure

      1073
    • 42.6.13 Fault Output

      1073
    • 42.6.14 Register Write Protection

      1074
  • 42.7 Analog-to-Digital Converter (ADC) User Interface

    1075
    • 42.7.1 ADC Control Register

      1076
    • 42.7.2 ADC Mode Register

      1077
    • 42.7.3 ADC Channel Sequence 1 Register

      1080
    • 42.7.4 ADC Channel Sequence 2 Register

      1081
    • 42.7.5 ADC Channel Enable Register

      1082
    • 42.7.6 ADC Channel Disable Register

      1083
    • 42.7.7 ADC Channel Status Register

      1084
    • 42.7.8 ADC Last Converted Data Register

      1085
    • 42.7.9 ADC Interrupt Enable Register

      1086
    • 42.7.10 ADC Interrupt Disable Register

      1087
    • 42.7.11 ADC Interrupt Mask Register

      1088
    • 42.7.12 ADC Interrupt Status Register

      1089
    • 42.7.13 ADC Overrun Status Register

      1090
    • 42.7.14 ADC Extended Mode Register

      1091
    • 42.7.15 ADC Compare Window Register

      1092
    • 42.7.16 ADC Channel Gain Register

      1093
    • 42.7.17 ADC Channel Offset Register

      1094
    • 42.7.18 ADC Channel Data Register

      1095
    • 42.7.19 ADC Analog Control Register

      1096
    • 42.7.20 ADC Write Protection Mode Register

      1097
    • 42.7.21 ADC Write Protection Status Register

      1098
• 43. Digital-to-Analog Converter Controller (DACC)

  1099
  • 43.1 Description

    1099
  • 43.2 Embedded Characteristics

    1099
  • 43.3 Block Diagram

    1100
  • 43.4 Signal Description

    1100
  • 43.5 Product Dependencies

    1101
    • 43.5.1 Power Management

      1101
    • 43.5.2 Interrupt Sources

      1101
    • 43.5.3 Conversion Performances

      1101
  • 43.6 Functional Description

    1102
    • 43.6.1 Digital-to-Analog Conversion

      1102
    • 43.6.2 Conversion Results

      1102
    • 43.6.3 Conversion Triggers

      1102
    • 43.6.4 Conversion FIFO

      1102
    • 43.6.5 Channel Selection

      1102
    • 43.6.6 Sleep Mode

      1103
    • 43.6.7 DACC Timings

      1103
    • 43.6.8 Register Write Protection

      1104
  • 43.7 Digital-to-Analog Converter (DACC) User Interface

    1105
    • 43.7.1 DACC Control Register

      1106
    • 43.7.2 DACC Mode Register

      1107
    • 43.7.3 DACC Channel Enable Register

      1111
    • 43.7.4 DACC Channel Disable Register

      1112
    • 43.7.5 DACC Channel Status Register

      1113
    • 43.7.6 DACC Conversion Data Register

      1114
    • 43.7.7 DACC Interrupt Enable Register

      1115
    • 43.7.8 DACC Interrupt Disable Register

      1116
    • 43.7.9 DACC Interrupt Mask Register

      1117
    • 43.7.10 DACC Interrupt Status Register

      1118
    • 43.7.11 DACC Analog Current Register

      1119
    • 43.7.12 DACC Write Protection Mode Register

      1120
    • 43.7.13 DACC Write Protection Status Register

      1121
• 44. Electrical Characteristics

  1122
  • 44.1 Absolute Maximum Ratings

    1122
  • 44.2 Recommended Opeating Conditions

    1122
  • 44.3 DC Characteristics

    1123
  • 44.4 Power Consumption

    1129
    • 44.4.1 Backup Mode Current Consumption

      1129
      • 44.4.1.1 Configuration A: Embedded Slow Clock RC Oscillator Enabled

        1129
      • 44.4.1.2 Configuration B: 32768 kHz Crystal Oscillator Enabled

        1129
    • 44.4.2 Sleep and Wait Mode Current Consumption

      1131
      • 44.4.2.1 Sleep Mode

        1131
      • 44.4.2.2 Wait Mode

        1137
    • 44.4.3 Active Mode Power Consumption

      1139
      • 44.4.3.1 SAM4S4/2 Active Power Consumption

        1140
      • 44.4.3.2 SAM4S16/S8 Active Power Consumption

        1140
      • 44.4.3.3 SAM4SD32/SD16/SA16 Active Power Consumption

        1142
    • 44.4.4 Peripheral Power Consumption in Active Mode

      1143
  • 44.5 Oscillator Characteristics

    1144
    • 44.5.1 32 kHz RC Oscillator Characteristics

      1144
    • 44.5.2 4/8/12 MHz RC Oscillators Characteristics

      1144
    • 44.5.3 32.768 kHz Crystal Oscillator Characteristics

      1145
    • 44.5.4 32.768 kHz Crystal Characteristics

      1145
    • 44.5.5 3 to 20 MHz Crystal Oscillator Characteristics

      1146
    • 44.5.6 3 to 20 MHz Crystal Characteristics

      1147
    • 44.5.7 3 to 20 MHz XIN Clock Input Characteristics in Bypass Mode

      1147
    • 44.5.8 Crystal Oscillator Design Considerations Information

      1148
      • 44.5.8.1 Choosing a Crystal

        1148
      • 44.5.8.2 Printed Circuit Board (PCB)

        1148
  • 44.6 PLLA, PLLB Characteristics

    1149
  • 44.7 USB Transceiver Characteristics

    1150
    • 44.7.1 Typical Connection

      1150
    • 44.7.2 Electrical Parameters

      1151
    • 44.7.3 Switching Characteristics

      1151
  • 44.8 12-bit ADC Characteristics

    1153
    • 44.8.1 ADC Power Supply

      1153
      • 44.8.1.1 ADC Bias Current

        1153
    • 44.8.2 External Reference Voltage

      1154
    • 44.8.3 ADC Timings

      1154
    • 44.8.4 ADC Transfer Function

      1155
      • 44.8.4.1 Differential Mode

        1155
      • 44.8.4.2 Single-ended Mode

        1155
      • 44.8.4.3 Example of LSB Computation

        1156
    • 44.8.5 ADC Electrical Characteristics

      1156
      • 44.8.5.1 Gain and Offset Errors

        1156
        • Differential Mode

          1157
        • Single-ended Mode

          1158
      • 44.8.5.2 ADC Electrical Performances

        1159
        • Single-ended Static Performances

          1159
        • Single-ended Dynamic Performances

          1159
        • Differential Static Performances

          1159
        • Differential Dynamic Performances

          1159
        • 10-bit ADC Mode

          1159
        • Low Voltage Supply

          1160
      • 44.8.5.3 ADC Channel Input Impedance

        1160
        • Track and Hold Time versus Source Output Impedance

          1161
  • 44.9 12-bit DAC Characteristics

    1162
  • 44.10 Analog Comparator Characteristics

    1164
  • 44.11 Temperature Sensor

    1164
  • 44.12 AC Characteristics

    1165
    • 44.12.1 Master Clock Characteristics

      1165
    • 44.12.2 I/O Characteristics

      1165
    • 44.12.3 SPI Characteristics

      1166
      • 44.12.3.1 Maximum SPI Frequency

        1167
      • 44.12.3.2 SPI Timings

        1168
    • 44.12.4 HSMCI Timings

      1168
    • 44.12.5 SSC Timings

      1169
    • 44.12.6 SMC Timings

      1173
      • 44.12.6.1 Read Timings

        1173
      • 44.12.6.2 Write Timings

        1175
    • 44.12.7 USART in SPI Mode Timings

      1178
      • 44.12.7.1 USART SPI TImings

        1180
    • 44.12.8 Two-wire Serial Interface Characteristics

      1181
    • 44.12.9 Embedded Flash Characteristics

      1183
• 45. Mechanical Characteristics

  1184
  • 45.1 Soldering Profile

    1195
  • 45.2 Packaging Resources

    1195
• 46. Errata

  1196
  • 46.1 Errata SAM4SD32/SD16/SA16/S16/S8 Rev. A Parts

    1196
    • 46.1.1 Flash Controller

      1196
      • 46.1.1.1 EFC: Flash Buffer not Cleared

        1196
      • 46.1.1.2 EFC: Code Loop Optimization Cannot Be Disabled

        1196
      • 46.1.1.3 EFC: Erase Sector Command cannot be performed if a sub-sector is locked (ONLY in Flash Sector0 ).

        1196
    • 46.1.2 Flash

      1197
      • 46.1.2.1 Flash: Incorrect Flash Read May Occur Depending on VDDIO Voltage and Flash Wait State

        1197
      • 46.1.2.2 Flash: Read Error after a GPNVM or Lock Bit Writing

        1197
    • 46.1.3 Watchdog

      1197
      • 46.1.3.1 Watchdog Not Stopped in Wait Mode

        1197
    • 46.1.4 Brownout Detector

      1198
      • 46.1.4.1 Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected

        1198
  • 46.2 Errata SAM4S4/S2 Rev. A Parts

    1199
    • 46.2.1 Flash Controller

      1199
      • 46.2.1.1 EFC: Erase Sector (ES) command cannot be performed if a subsector is locked (ONLY in Flash sector 0)

        1199
    • 46.2.2 Flash

      1199
      • 46.2.2.1 Flash: Incorrect Flash Read May Occur Depending on VDDIO Voltage and Flash Wait State

        1199
    • 46.2.3 Brownout Detector

      1200
      • 46.2.3.1 Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected

        1200
• 47. Ordering Information

  1201
• 48. Revision History

  1205
• Table of Contents

  1223