AMD athlon 64 Manuale Utente
Chapter 2
Experimental Setup
15
Performance Guidelines for AMD Athlon™ 64 and AMD Opteron™
ccNUMA Multiprocessor Systems
40555
Rev. 3.00
June 2006
Figure 2.
Internal Resources Associated with a Quartet Node
From the perspective of the MCT, a memory request may come from either the local core or from
another core over a coherent HyperTransport link. The former request is a local request, while the
latter is a remote request. In the former case, the request could be routed from the local core to the
SRI, then to the XBar and then to the MCT. In the later case, the request is routed from the remote
core over the coherent HyperTransport link to the XBar and from there to the MCT.
another core over a coherent HyperTransport link. The former request is a local request, while the
latter is a remote request. In the former case, the request could be routed from the local core to the
SRI, then to the XBar and then to the MCT. In the later case, the request is routed from the remote
core over the coherent HyperTransport link to the XBar and from there to the MCT.
The MCT, the SRI and the XBar on each node all have internal buffers that are used to queue
transaction packets for transmission. For additional details on the Northbridge buffer queues, refer to
Section A.1 on page 39.
transaction packets for transmission. For additional details on the Northbridge buffer queues, refer to
Section A.1 on page 39.
From a system perspective, the developer can think of the system as having three key resources that
affect throughput: memory bandwidth, HyperTransport bandwidth and buffer queue capacity.
affect throughput: memory bandwidth, HyperTransport bandwidth and buffer queue capacity.
2.2
Synthetic Test
The test used is a simple synthetic workload consisting of two threads with each thread accessing an
array that is not shared with the other thread. The time taken by each thread to access this array is
measured.
array that is not shared with the other thread. The time taken by each thread to access this array is
measured.
Each thread does a series of read-only or write-only accesses to successive elements of the array using
a cache line stride (64 bytes). The test iterates through all permutations of read-read, read-write,
write-read, and write-write for the access patterns of the two threads. Each array is sized at 64MB—
significantly larger than the cache size.
a cache line stride (64 bytes). The test iterates through all permutations of read-read, read-write,
write-read, and write-write for the access patterns of the two threads. Each array is sized at 64MB—
significantly larger than the cache size.
This synthetic test is neither a pure memory latency test nor a pure memory bandwidth test; rather it
places varying throughput and capacity demands on the resources of the system described in the
previous section. This provides an understanding of how the system behaves when any of the
places varying throughput and capacity demands on the resources of the system described in the
previous section. This provides an understanding of how the system behaves when any of the
4 GV/s per direction
@ 2 GHz Data Rate
@ 2 GHz Data Rate
4 GV/s per direction
@ 2 GHz Data Rate
@ 2 GHz Data Rate
HT = HyperTransport™ Technology
C0
C1
4 GV/s per direction
@ 2 GHz Data Rate
@ 2 GHz Data Rate