AMD athlon 64 Manuale Utente
14
Experimental Setup
Chapter 2
40555
Rev. 3.00
June 2006
Performance Guidelines for AMD Athlon™ 64 and AMD Opteron™
ccNUMA Multiprocessor Systems
ccNUMA Multiprocessor Systems
Figure 1.
Quartet Topology
The term hop is commonly used to describe access distances on NUMA systems. When a thread
accesses memory on the same node as that on which it is running, it is a 0-hop access or local access.
If a thread is running on one node but accessing memory that is resident on a different node, the
access is a remote access. If the node on which the thread is running and the node on which the
memory resides are directly connected to each other, the memory access is a 1-hop access. If they are
indirectly connected to each other (i.e., there is no direct coherent HyperTransport link) in the 4P
configuration shown in Figure 1, the memory access is a 2-hop access. For example, if a thread
running on Node 0 (N0) accesses memory resident on Node 3 (N3), the memory access is a 2-hop
access.
accesses memory on the same node as that on which it is running, it is a 0-hop access or local access.
If a thread is running on one node but accessing memory that is resident on a different node, the
access is a remote access. If the node on which the thread is running and the node on which the
memory resides are directly connected to each other, the memory access is a 1-hop access. If they are
indirectly connected to each other (i.e., there is no direct coherent HyperTransport link) in the 4P
configuration shown in Figure 1, the memory access is a 2-hop access. For example, if a thread
running on Node 0 (N0) accesses memory resident on Node 3 (N3), the memory access is a 2-hop
access.
Figure 2 on page 15 views the resources of each node from a lower level perspective. Each (dual-
core) processor has two cores. The two cores talk to a system request interface (SRI), which in turn
talks to a crossbar (XBar). The crossbar is connected to the local memory controller (MCT) on one
end and to the various HyperTransport links on the other end. The SRI, XBar and MCT are
collectively called the Northbridge on the node. The MCT is connected to the physical memory
(DRAM) for that node.
core) processor has two cores. The two cores talk to a system request interface (SRI), which in turn
talks to a crossbar (XBar). The crossbar is connected to the local memory controller (MCT) on one
end and to the various HyperTransport links on the other end. The SRI, XBar and MCT are
collectively called the Northbridge on the node. The MCT is connected to the physical memory
(DRAM) for that node.
N0
N1
N2
N3
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