Техническая Спецификация для Infineon Technologies KITXMC2GOXMC1100V1TOBO1
XMC1100
XMC1000 Family
Electrical Parameter
Data Sheet
43
V1.4, 2014-05
3.3.5
Serial Wire Debug Port (SW-DP) Timing
The following parameters are applicable for communication through the SW-DP
interface.
interface.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Figure 14
SWD Timing
Table 21
SWD Interface Timing Parameters(Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
SWDCLK high time
t
1
SR
50
–
500000 ns
–
SWDCLK low time
t
2
SR
50
–
500000 ns
–
SWDIO input setup
to SWDCLK rising edge
to SWDCLK rising edge
t
3
SR
10
–
–
ns
–
SWDIO input hold
after SWDCLK rising edge
after SWDCLK rising edge
t
4
SR
10
–
–
ns
–
SWDIO output valid time
after SWDCLK rising edge
after SWDCLK rising edge
t
5
CC –
–
68
ns
C
L
= 50 pF
–
–
62
ns
C
L
= 30 pF
SWDIO output hold time
from SWDCLK rising edge
from SWDCLK rising edge
t
6
CC 4
–
–
ns
SWDCLK
SWDIO
(Output )
t
1
t
2
t
6
t
5
SWDIO
(Input )
t
3
t
4
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