Техническая Спецификация для Infineon Technologies KITXMC2GOXMC1100V1TOBO1
XMC1100
XMC1000 Family
Electrical Parameter
Data Sheet
44
V1.4, 2014-05
3.3.6
SPD Timing Requirements
The optimum SPD decision time between 0
B
and 1
B
is 0.75 µs. With this value the
system has maximum robustness against frequency deviations of the sampling clock on
tool and on device side. However it is not always possible to exactly match this value
with the given constraints for the sample clock. For instance for a oversampling rate of
4, the sample clock will be 8 MHz and in this case the closest possible effective decision
time is 5.5 clock cycles (0.69 µs).
tool and on device side. However it is not always possible to exactly match this value
with the given constraints for the sample clock. For instance for a oversampling rate of
4, the sample clock will be 8 MHz and in this case the closest possible effective decision
time is 5.5 clock cycles (0.69 µs).
For a balanced distribution of the timing robustness of SPD between tool and device, the
timing requirements for the tool are:
timing requirements for the tool are:
•
Frequency deviation of the sample clock is +/- 5%
•
Effective decision time is between 0.69 µs and 0.75 µs (calculated with nominal
sample frequency)
sample frequency)
Table 22
Optimum Number of Sample Clocks for SPD
Sample
Freq.
Freq.
Sampling
Factor
Factor
Sample
Clocks 0
Clocks 0
B
Sample
Clocks 1
Clocks 1
B
Effective
Decision
Time
Decision
Time
1)
1) Nominal sample frequency period multiplied with 0.5 + (max. number of 0
B
sample clocks)
Remark
8 MHz
4
1 to 5
6 to 12
0.69 µs
The other closest option
(0.81 µs) for the effective
decision time is less robust.
(0.81 µs) for the effective
decision time is less robust.
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