Epson S1D13708 Benutzerhandbuch

Page 10

Vancouver Design Center

S1D13708

Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor

X39A-G-010-01

Issue Date: 01/11/25

caches from program or data memory. They are typically not used for transfers to or from 
IO peripheral devices such as the S1D13708. The MCF5307 chip selects provide a 
mechanism to disable burst accesses for peripheral devices which are not burst capable.

In addition to generating eight independent chip-select outputs, the MCF5307 Chip Select 
Module can generate active-low Output Enable (OE) and Write Enable (BWE) signals 
compatible with most memory and x86-style peripherals. The MCF5307 bus controller also 
provides a Read/Write (R/W) signal which is compatible with most 68K peripherals.

Chip selects 0 and 1 can be programmed independently to respond to any base address and 
block size. Chip select 0 can be active immediately after reset, and is typically used to 
control a boot ROM. Chip select 1 is likewise typically used to control a large static or 
dynamic RAM block.

Chip selects 2 through 7 have fixed block sizes of 2M bytes each. Each has a unique, fixed 
offset from a common, programmable starting address. These chip selects are well-suited 
to typical IO addressing requirements.

Each chip select may be individually programmed for:

• port size (8/16/32-bit).

• up to 15 wait states or external acknowledge.

• address space type.

• burst or non-burst cycle support.

• write protect.

Figure 2-3: “Chip Select Module Outputs Timing”  illustrates a typical cycle for a memory 
mapped device using the GPCM of the Power PC.

CLK

CS[7:0]

BE/BWE[3:0]

OE