Epson S1D13708 Benutzerhandbuch
Epson Research and Development
Page 9
Vancouver Design Center
Interfacing to 8-bit Processors
S1D13708
Issue Date: 01/11/25
X39A-G-015-01
3 S1D13708 Host Bus Interface
The S1D13708 directly supports multiple processors. The S1D13708 implements a 16-bit
Generic #2 Host Bus Interface which can be adapted for use with an 8-bit processor.
Generic #2 Host Bus Interface which can be adapted for use with an 8-bit processor.
The Generic #2 Host Bus Interface is selected by the S1D13708 on the rising edge of
RESET#. After RESET# is released, the bus interface signals assume their selected config-
uration. For details on the S1D13708 configuration, see Section 4.2, “S1D13708 Hardware
Configuration” on page 12.
RESET#. After RESET# is released, the bus interface signals assume their selected config-
uration. For details on the S1D13708 configuration, see Section 4.2, “S1D13708 Hardware
Configuration” on page 12.
The S1D13708 clock (CLKI) is taken from the system host bus. The system clock source
will drive all required internal clocks. If they are not used, the CLKI2 and XTAL inputs
should be tied to ground.
will drive all required internal clocks. If they are not used, the CLKI2 and XTAL inputs
should be tied to ground.
3.1 Host Bus Interface Pin Mapping
The following table shows the functions of each Host Bus Interface signal.
Table 3-1: Host Bus Interface Pin Mapping
S1D13708
Pin Names
Generic #2
Comments
AB[16:0]
A[16:0]
—
DB[15:0]
D[15:0]
—
WE1#
Byte High Enable (BHE#)
External decode required
CS#
Chip Select
External decode required
M/R#
Memory/Register Select
External decode required
CLKI
BUSCLK
—
BS#
connect to IO V
DD
—
RD/WR#
connect to IO V
DD
—
RD#
RD#
—
WE0#
WE#
—
WAIT#
WAIT#
—
RESET#
Inverted RESET
—