Epson S1D13708 Benutzerhandbuch

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Vancouver Design Center

S1D13708

Interfacing to 8-bit Processors

X39A-G-015-01

Issue Date: 01/11/25

The S1D13708 Generic #2 Host Bus Interface requires the following signals from an 8-bit 
processor.

• CLKI is a clock input which is required by the S1D13708 Host Bus Interface as a source 

for its internal bus and memory clocks. This clock is typically driven by the host CPU 
system clock.

• The address inputs AB[16:0] connect directly to the 8-bit processor address lines 

(A[16:0). If the specific 8-bit processor cannot implement all 17 address lines required 
by the S1D13708, only a portion of the 80K byte S1D13708 display buffer is accessible. 
For example, if only AB[15:0] are supported, only the first 64K byte of the display 
buffer is available.

• The data bus DB[15:0] must be connected so that the 8-bit processor data lines (D[7:0]) 

are connected to both DB[15:8] and DB[7:0] of the S1D13708. CNF4 must be set to 
select little endian mode.

• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper 

register and memory address space.

• M/R# (memory/register) selects between memory or register accesses. This signal may 

be connected to an address line, allowing system address A17 to be connected to the 
M/R# line.

If A17 is unavailable on the 8-bit processor, an external decode must be used to gen-
erate the M/R# signal.

• BHE# is the high byte enable for both read and write cycles and connects to the high 

byte chip select signal.

In an 8-bit environment, this signal is driven by inverting address line A0 thus indi-
cating that odd addresses are to be read/write on the high byte of the data bus.

• WE# connects to WE# (the write enable signal) and must be driven low when the 8-bit 

processor is writing data to the S1D13708. 

• RD# connects to RD# (the read enable signal) and must be driven low when the 8-bit 

processor is reading data from the S1D13708. 

• WAIT# is a signal output from the S1D13708 that indicates the 8-bit processor must 

wait until data is ready (read cycle) or accepted (write cycle) on the host bus. Since host 
CPU bus accesses to the S1D13708 may occur asynchronously to the display update, it 
is possible that contention may occur in accessing the 13708 internal registers and/or 
display buffer. The WAIT# line resolves these contentions by forcing the host to wait 
until the resource arbitration is complete. This signal is active low and may need to be 
inverted if the host CPU wait state signal is active high.

• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in this implemen-

tation of a generic 8-bit processor using the Generic #2 Host Bus Interface. These pins 
must be tied high (connected to IO V

DD

).