Texas Instruments TMS320C64x DSP Benutzerhandbuch
Capturing Video in BT.656 or Y/C Mode
Video Capture Port
3-44
SPRU629
3.10 Capturing Video in BT.656 or Y/C Mode
In order to capture video in the BT.656 or Y/C format, the following steps are
needed:
needed:
1) Set the last pixel to be captured in VCxSTOP1 and VCxSTOP2 (set the
VCXSTOP and VCYSTOP bits).
2) Set the first pixel to be captured in VCxSTRT1 and VCxSTRT2 (set the
VCXSTART and VCYSTART bits).
3) Write to VCxTHRLD to set the capture threshold. Every time the number
of received pixels reaches the number specified by the VCTHRLD1 bits,
a YEVTx, CbEVTx, and CrEVTx are generated by the video capture
module. The VCTHRLD1 bits value must be an even number.
a YEVTx, CbEVTx, and CrEVTx are generated by the video capture
module. The VCTHRLD1 bits value must be an even number.
4) Configure a DMA channel to move data from YSRCx to a destination in
the DSP memory. The channel transfers should be triggered by the
YEVTx. The size of the transfers should be set to VCTHRLD1/4 for 8-bit
mode, VCTHRLD1/2 for 10-bit mode, or VCTHRLD1/3 for dense 10-bit
mode. (This is because 4, 2, or 3 pixels are packed per FIFO word and the
DMA is moving 32-bit words from YSRCx to the memory). The DMA must
start on a doubleword boundary and move an even number of words.
YEVTx. The size of the transfers should be set to VCTHRLD1/4 for 8-bit
mode, VCTHRLD1/2 for 10-bit mode, or VCTHRLD1/3 for dense 10-bit
mode. (This is because 4, 2, or 3 pixels are packed per FIFO word and the
DMA is moving 32-bit words from YSRCx to the memory). The DMA must
start on a doubleword boundary and move an even number of words.
5) Configure a DMA channel to move data from CBSRCx to a destination in
the DSP memory. The channel transfers should be triggered by the
CbEVTx. The size of the transfers should be set to VCTHRLD1/8 for 8-bit
mode, VCTHRLD1/4 for 10-bit mode, or VCTHRLD1/6 for dense 10-bit
mode. (This is because 4, 2, or 3 pixels are packed per FIFO word, the
DMA is moving 32-bit words from CBSRCx to the memory, and there are
half the number of pixels in the Cb FIFO as in the Y FIFO.) The DMA must
start on a doubleword boundary and move an even number of words.
CbEVTx. The size of the transfers should be set to VCTHRLD1/8 for 8-bit
mode, VCTHRLD1/4 for 10-bit mode, or VCTHRLD1/6 for dense 10-bit
mode. (This is because 4, 2, or 3 pixels are packed per FIFO word, the
DMA is moving 32-bit words from CBSRCx to the memory, and there are
half the number of pixels in the Cb FIFO as in the Y FIFO.) The DMA must
start on a doubleword boundary and move an even number of words.
6) Configure a DMA channel to move data from CRSRCx to a destination in
the DSP memory. The channel transfers should be triggered by the
CrEVTx. The size of the transfers should be set to VCTHRLD1/8 for 8-bit
mode, VCTHRLD1/4 for 10-bit mode, or VCTHRLD1/6 for dense 10-bit
mode. (This is because 4, 2, or 3 pixels are packed per FIFO word, the
DMA is moving 32-bit words from CRSRCx to the memory, and there are
half the number of pixels in the Cr FIFO as in the Y FIFO.) The DMA must
start on a double-word boundary and move an even number of words.
CrEVTx. The size of the transfers should be set to VCTHRLD1/8 for 8-bit
mode, VCTHRLD1/4 for 10-bit mode, or VCTHRLD1/6 for dense 10-bit
mode. (This is because 4, 2, or 3 pixels are packed per FIFO word, the
DMA is moving 32-bit words from CRSRCx to the memory, and there are
half the number of pixels in the Cr FIFO as in the Y FIFO.) The DMA must
start on a double-word boundary and move an even number of words.
7) Write to the video port interrupt enable register (VPIE) to enable overrun
(COVRx) and capture complete (CCMPx) interrupts, if desired.