Texas Instruments TMS320C64x DSP Benutzerhandbuch
Capturing Video in BT.656 or Y/C Mode
3-45
Video Capture Port
SPRU629
8) Write to VCxCTL to:
-
Set capture mode (CMODE = 00x for BT.656 input, 10x for Y/C input).
-
Set desired field/frame operation (CON, FRAME, CF2, CF1 bits).
-
Set sync and field ID control (VRST, HRST, FDD, FINV, VCTL1 bits).
-
Set 10-bit pack mode (10BPK bits), if 10-bit operation is selected.
-
Enable scaling (SCALE and RESMPL bits), if desired and using 8-bit
data.
data.
-
Set VCEN bit to enable capture.
9) Capture is enabled at the start of the first frame after VCEN = 1 and begins
at the start of the first selected field. DMA events are generated as
triggered by VCxTHRLD1. When a selected field has been captured
(VCXPOS = VCXSTOP and VCYPOS = VCYSTOP), the F1C, F2C, or
FRMC bits in VCxSTAT are set and cause the CCMPx bit in VPIS to be set.
This generates a DSP interrupt, if the CCMPx bit is enabled in VPIE.
triggered by VCxTHRLD1. When a selected field has been captured
(VCXPOS = VCXSTOP and VCYPOS = VCYSTOP), the F1C, F2C, or
FRMC bits in VCxSTAT are set and cause the CCMPx bit in VPIS to be set.
This generates a DSP interrupt, if the CCMPx bit is enabled in VPIE.
10) If continuous capture is enabled, the video port begins capturing again at
the start of the next selected field or frame. If noncontinuous field 1 and
field 2 or frame capture is enabled, the next field or frame is captured,
during which the DSP must clear the appropriate completion status bit or
further capture is disabled. If single frame capture is enabled, capture is
disabled until the DSP clears the FRMC bit.
field 2 or frame capture is enabled, the next field or frame is captured,
during which the DSP must clear the appropriate completion status bit or
further capture is disabled. If single frame capture is enabled, capture is
disabled until the DSP clears the FRMC bit.
3.10.1 Handling FIFO Overrun in BT.656 or Y/C Mode
In case of a FIFO overrun, the COVRx bit is set in VPIS. This condition initiates
an interrupt to the DSP, if the overrun interrupt is enabled (setting the COVR
bit in VPIE enables overrun interrupt).
an interrupt to the DSP, if the overrun interrupt is enabled (setting the COVR
bit in VPIE enables overrun interrupt).
The overrun interrupt routine should set the BLKCAP bit in VCxCTL and it
should reconfigure DMA channel settings. The DMA channel must be reconfi-
gured for capture of the next frame since the current frame transfer failed. Set-
ting the BLKCAP bit flushes the capture FIFO and blocks DMA events for the
channel. As long as the BLKCAP bit is set, the video capture channel ignores
the incoming data with exception of SAV and EAV codes but the internal counters
continue counting.
should reconfigure DMA channel settings. The DMA channel must be reconfi-
gured for capture of the next frame since the current frame transfer failed. Set-
ting the BLKCAP bit flushes the capture FIFO and blocks DMA events for the
channel. As long as the BLKCAP bit is set, the video capture channel ignores
the incoming data with exception of SAV and EAV codes but the internal counters
continue counting.
The BLKCAP bit should be cleared to 0 in order to continue capture. Clearing
the BLKCAP bit takes effect in the subsequent video field (DMA events are still
going to be blocked in the video field in which the BLKCAP bit is cleared.)
the BLKCAP bit takes effect in the subsequent video field (DMA events are still
going to be blocked in the video field in which the BLKCAP bit is cleared.)