Texas Instruments TMS320C64x DSP Benutzerhandbuch
Video Display Registers
Video Display Port
4-52
SPRU629
4.12 Video Display Registers
The registers for controlling the video display mode of operation are listed in
Table 4–5. See the device-specific datasheet for the memory address of these
registers.
Table 4–5. See the device-specific datasheet for the memory address of these
registers.
Table 4–5. Video Display Control Registers
Acronym
Register Name
Section
VDSTAT
Video Display Status Register
VDCTL
Video Display Control Register
VDFRMSZ
Video Display Frame Size Register
VDHBLNK
Video Display Horizontal Blanking Register
VDVBLKS1
Video Display Field 1 Vertical Blanking Start Register
VDVBLKE1
Video Display Field 1 Vertical Blanking End Register
VDVBLKS2
Video Display Field 2 Vertical Blanking Start Register
VDVBLKE2
Video Display Field 2 Vertical Blanking End Register
VDIMGOFF1
Video Display Field 1 Image Offset Register
VDIMGSZ1
Video Display Field 1 Image Size Register
VDIMGOFF2
Video Display Field 2 Image Offset Register
VDIMGSZ2
Video Display Field 2 Image Size Register
VDFLDT1
Video Display Field 1 Timing Register
VDFLDT2
Video Display Field 2 Timing Register
VDTHRLD
Video Display Threshold Register
VDHSYNC
Video Display Horizontal Synchronization Register
VDVSYNS1
Video Display Field 1 Vertical Synchronization Start Register
VDVSYNE1
Video Display Field 1 Vertical Synchronization End Register
VDVSYNS2
Video Display Field 2 Vertical Synchronization Start Register
VDVSYNE2
Video Display Field 2 Vertical Synchronization End Register
VDRELOAD
Video Display Counter Reload Register
VDDISPEVT
Video Display Display Event Register
VDCLIP
Video Display Clipping Register