Texas Instruments TMS320C64x DSP Benutzerhandbuch
Video Display Registers
4-53
Video Display Port
SPRU629
Table 4–5. Video Display Control Registers (Continued)
Acronym
Section
Register Name
VDDEFVAL
Video Display Default Display Value Register
VDVINT
Video Display Vertical Interrupt Register
VDFBIT
Video Display Field Bit Register
VDVBIT1
Video Display Field 1 Vertical Blanking Bit Register
VDVBIT2
Video Display Field 2 Vertical Blanking Bit Register
4.12.1 Video Display Status Register (VDSTAT)
The video display status register (VDSTAT) indicates the current display status
of the video port. The VDSTAT is shown in Figure 4–39 and described in
Table 4–6.
of the video port. The VDSTAT is shown in Figure 4–39 and described in
Table 4–6.
The VDXPOS and VDYPOS bits track the coordinates of the most-recently
displayed pixel. The F1D, F2D, and FRMD bits indicate the completion of fields
or frames and may need to be cleared by the DSP to prevent a DCNA interrupt
from being generated, depending on the selected frame operation. The F1D,
F2D, and FRMD bits are set when the final pixel from the appropriate field has
been sent to the output pad.
displayed pixel. The F1D, F2D, and FRMD bits indicate the completion of fields
or frames and may need to be cleared by the DSP to prevent a DCNA interrupt
from being generated, depending on the selected frame operation. The F1D,
F2D, and FRMD bits are set when the final pixel from the appropriate field has
been sent to the output pad.
Figure 4–39. Video Display Status Register (VDSTAT)
31
30
29
28
27
16
—
FRMD
F2D
F1D
VDYPOS
R-0
R/WC-0
R/WC-0
R/WC-0
R-0
15
14
13
12
11
0
Reserved
VBLNK
VDFLD
VDXPOS
R-0
R-0
R-0
R-0
Legend: R = Read only; WC = Write 1 to clear, write of 0 has no effect; -n = value after reset