Texas Instruments TMS320C64x DSP Benutzerhandbuch

4-74

The video display field 1 timing register (VDFLDT1) sets the timing of the field
identification signal. The VDFLDT1 is shown in Figure 4–51 and described in
Table 4–18.

In raw data mode, the FLD signal is deasserted to indicate field 1 display
whenever the frame line counter (FLCOUNT) is equal to FLD1YSTART and
the frame pixel counter (FPCOUNT) is equal to FLD1XSTART (this is shown
in Figure 4–6, page 4-7).

In BT.656 and Y/C mode, the FLD signal is deasserted to indicate field 1 dis-
play whenever FLCOUNT = FLD1YSTART and FPCOUNT = FLD1XSTART.
The FLD output is completely independent of the timing control codes. The
F bit in the EAV/SAV codes is controlled by the VDFBIT register.

31

28

27

16

Reserved

FLD1YSTART

R-0

R/W-0

15

12

11

0

Reserved

FLD1XSTART

R-0

R/W-0

Legend: R = Read only; R/W = Read/Write; -n = value after reset

†

†

31–28

Reserved

–

0

Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.

27–16

FLD1YSTART

OF(value)

0–FFFh

Specifies the first line of field 1. (The line where FLD is
deasserted.)

15–12

Reserved

–

0

Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.

11–0

FLD1XSTART

OF(value)

0–FFFh

Specifies the pixel on the first line of field 1 where the FLD
output is deasserted.

† For CSL implementation, use the notation VP_VDFLDT1_field_symval