Texas Instruments TMS320C64x DSP Benutzerhandbuch
Video Display Registers
Video Display Port
4-76
SPRU629
4.12.15
Video Display Threshold Register (VDTHRLD)
The video display threshold register (VDTHRLD) sets the display FIFO thresh-
old to determine when to load more display data. The VDTHRLD is shown in
Figure 4–53 and described in Table 4–20.
old to determine when to load more display data. The VDTHRLD is shown in
Figure 4–53 and described in Table 4–20.
The VDTHRLDn bits determines how much space must be available in the
display FIFOs before the appropriate DMA event may be generated. The
Y FIFO uses the VDTHRLDn value directly while the Cb and Cr values use
display FIFOs before the appropriate DMA event may be generated. The
Y FIFO uses the VDTHRLDn value directly while the Cb and Cr values use
½
the VDTHRLDn value rounded up to the next doubleword
(1/2 (VDTHRLDn + VTHRLDn mod 2). The DMA transfer size must be less
than the value used for each FIFO. Typically, VDTHRLDn is set to the horizontal
line length rounded up to the next doubleword boundary. For nonline length
thresholds, the display data unpacking mechanism places certain restrictions
of what VDTHRLDn values are valid (see section 2.3.3).
than the value used for each FIFO. Typically, VDTHRLDn is set to the horizontal
line length rounded up to the next doubleword boundary. For nonline length
thresholds, the display data unpacking mechanism places certain restrictions
of what VDTHRLDn values are valid (see section 2.3.3).
The VDTHRLD2 bits behaves identically to VDTHRLD1, but are used during
field 2 capture. It is only used if the field 2 DMA size needs to be different from
the field 1 DMA size for some reason (for example, different display line
lengths in field 1 and field 2).
field 2 capture. It is only used if the field 2 DMA size needs to be different from
the field 1 DMA size for some reason (for example, different display line
lengths in field 1 and field 2).
In raw display mode, the INCPIX bits determine when the frame pixel counter
(FPCOUNT) is incremented . If, for example, each output value represents the
R, G, or B portion of a display pixel, then the INCPIX bits are set to 3h so that
the pixel counter is incremented only on every third output clock. An INCPIX
value of 0h represents a count of 16 rather than 0.
(FPCOUNT) is incremented . If, for example, each output value represents the
R, G, or B portion of a display pixel, then the INCPIX bits are set to 3h so that
the pixel counter is incremented only on every third output clock. An INCPIX
value of 0h represents a count of 16 rather than 0.
Figure 4–53. Video Display Threshold Register (VDTHRLD)
31
26
25
16
Reserved
VDTHRLD2
R-0
R/W-0
15
12
11
10
9
0
INCPIX
Reserved
VDTHRLD1
R/W-0001
R-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset