Texas Instruments TMS320C64x DSP Benutzerhandbuch
BT.656 Video Capture Mode
Video Capture Port
3-8
SPRU629
For the BT.656 video capture mode, the FIFO buffer is divided into three sec-
tions (three buffers). One section is 1280 bytes deep and is dedicated for stor-
age of Y data samples. The other two sections are dedicated for storage of Cb
and Cr data samples, respectively. The buffers for Cb and Cr samples are each
640 bytes deep. The incoming video data stream is separated into Y, Cb, and
Cr data streams, scaled (if selected), and the Y, Cb, and Cr buffers are filled.
Each of the three buffers has a memory-mapped location associated with it;
YSRC, CBSRC, and CRSRC. The YSRC, CBSRC, and CRSRC locations are
read only and are used by DMAs to access video data samples stored in the
FIFOs.
tions (three buffers). One section is 1280 bytes deep and is dedicated for stor-
age of Y data samples. The other two sections are dedicated for storage of Cb
and Cr data samples, respectively. The buffers for Cb and Cr samples are each
640 bytes deep. The incoming video data stream is separated into Y, Cb, and
Cr data streams, scaled (if selected), and the Y, Cb, and Cr buffers are filled.
Each of the three buffers has a memory-mapped location associated with it;
YSRC, CBSRC, and CRSRC. The YSRC, CBSRC, and CRSRC locations are
read only and are used by DMAs to access video data samples stored in the
FIFOs.
If video capture is enabled (BLKCAP bit in VCxCTL is cleared), pixels in the
capture window are captured in the Y, Cb, and Cr buffers. The video capture
module uses the YEVT, CbEVT, and CrEVT events to notify the DMA controller
to copy data from the capture buffers to the DSP memory. The number of
doublewords required to generate the events is set by the VCTHRLDn bits in
VCxTHRLD. On every YEVT, the DMA should move data from the Y buffer to
DSP memory using the YSRC location as the source address. On every
CbEVT, the DMA should move data from the Cb buffer to DSP memory using
the CBSRC location as the source address. On every CrEVT, the DMA should
move data from the Cr buffer to DSP memory using the CRSRC location as
the source address. Note that transfer size from the Cb and Cr buffers is half
of the transfer size from the Y buffer since for every four Y samples, there are
two Cb and two Cr samples.
capture window are captured in the Y, Cb, and Cr buffers. The video capture
module uses the YEVT, CbEVT, and CrEVT events to notify the DMA controller
to copy data from the capture buffers to the DSP memory. The number of
doublewords required to generate the events is set by the VCTHRLDn bits in
VCxTHRLD. On every YEVT, the DMA should move data from the Y buffer to
DSP memory using the YSRC location as the source address. On every
CbEVT, the DMA should move data from the Cb buffer to DSP memory using
the CBSRC location as the source address. On every CrEVT, the DMA should
move data from the Cr buffer to DSP memory using the CRSRC location as
the source address. Note that transfer size from the Cb and Cr buffers is half
of the transfer size from the Y buffer since for every four Y samples, there are
two Cb and two Cr samples.
3.2.4
BT.656 Data Sampling
Incoming data (including timing codes) are sampled and the HCOUNT counter
advanced only on clock cycles for which the CAPEN input is active. Inputs
when CAPEN is inactive are ignored. The timing reference codes are recognized
only when three sequential samples with CAPEN valid are the FFh, 00h, 00h
sequence. A non-00h sample after the FFh or after the first 00h causes the
timing reference recognition logic to be reset and to look for FFh again.
(Unsampled data; those with CAPEN inactive; in the middle of a timing reference
do not cause the recognition logic to be reset since these are not considered
to be valid inputs.)
advanced only on clock cycles for which the CAPEN input is active. Inputs
when CAPEN is inactive are ignored. The timing reference codes are recognized
only when three sequential samples with CAPEN valid are the FFh, 00h, 00h
sequence. A non-00h sample after the FFh or after the first 00h causes the
timing reference recognition logic to be reset and to look for FFh again.
(Unsampled data; those with CAPEN inactive; in the middle of a timing reference
do not cause the recognition logic to be reset since these are not considered
to be valid inputs.)