Texas Instruments TMS320C64x DSP Benutzerhandbuch
BT.656 Video Capture Mode
3-9
Video Capture Port
SPRU629
3.2.5
BT.656 FIFO Packing
Captured data is always packed into 64-bits before being written into the cap-
ture FIFO(s). The packing and byte ordering is dependant upon the capture
data size and the device endian mode. For little-endian operation (default),
data is packed into the FIFO from right to left; for big-endian operation, data
is packed from left to right.
ture FIFO(s). The packing and byte ordering is dependant upon the capture
data size and the device endian mode. For little-endian operation (default),
data is packed into the FIFO from right to left; for big-endian operation, data
is packed from left to right.
The 8-bit BT.656 mode uses three FIFOs for color separation. Four samples
are packed into each word as shown in Figure 3–2.
are packed into each word as shown in Figure 3–2.
Figure 3–2. 8-Bit BT.656 FIFO Packing
Cr 6
Cr 14
Cb 6
Cb 14
Y 6
Y 14
Y 22
Y 30
Cr 1
Cr 9
Cb 1
Cb 9
Y 1
Y 9
Y 17
Y 25
Cr 2
Cr FIFO
Cr 1
Cr 9
Cb 1
Cb 9
Y 1
Y 9
Y 17
Y 25
Cb 0
Cb FIFO
Cr 0
Cr 8
63
Cr FIFO
55
56
Cb 8
63
Y 0
Y 8
Y 16
Y 24
63
Y FIFO
55
56
55
56
Cr 3
Cr 11
Cb 3
Cb 11
Y 3
Y 11
Y 19
Y 27
Big-Endian Packing
Little-Endian Packing
Cb 2
Cr 2
Cr 10
48
47
40
39
Cb 10
Y 2
Y 10
Y 18
Y 26
48
47
48 47
40
39
39
40
Cb 4
Cb 5
Cr 5
Cr 13
23
Cr 4
Cr 12
31
32
24
15
16
Cb 13
23
Y 5
Y 13
Y 21
Y 29
23
Y 12
Cb 12
Y 4
31
32
24
Y 20
Y 28
31
32
24
15
16
15
16
Cr 6
Cr 14
Cb 6
Cb 14
Y 6
Y 14
Y 22
Y 30
Cb 0
Y 23
Cr 7
Cr 15
63
Cb 7
Cb 15
63
Y 7
Y 15
Cb FIFO
Y FIFO
55
56
55
56
Y 31
63
VCLKINA / VCLKINB
VDIN[9–2] / VDIN[9–12]
55
56
Cr 4
Cr 12
Cb 4
Cb 12
Y 4
Y 12
Y 20
Y 28
Y 2
Y 21
Cr 5
Cr 13
Cb 5
Cb 13
Y 5
Y 13
48 47
48 47
39
40
40
39
Y 29
Cr 0
Y 0
48 47
Cb 1
40
39
Y 1
Y 18
Y 19
Cr 2
Cr 10
23
Cb 2
Cb 10
23
Y 2
Y 10
Cb 11
Cr 3
Cr 11
Cb 3
31
32
24
Y 3
Y 11
31
32
24
15
16
15
16
Y 26
23
Y 3
Y 27
Cr 1
31
32
24
Y 4
Cb 2
15
16
Cb 7
Cr 7
Cr 15
8 7
0
Cb 15
Y 7
Y 15
Y 23
Y 31
8 7
8 7
0
0
Y 16
Cr 0
Cr 8
Cb 0
Cb 8
Y 0
Y 8
8 7
8 7
0
0
Y 24
Y 5
8 7
0