Texas Instruments TMS320C6747 DSP Benutzerhandbuch
3.18 HC Low-Speed Threshold Register (HCLSTHRESHOLD)
Registers
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The HC low-speed threshold register (HCLSTHRESHOLD) defines the latest time in a frame that the USB
host controller can begin a low-speed packet. HCLSTHRESHOLD is shown in
host controller can begin a low-speed packet. HCLSTHRESHOLD is shown in
and described in
.
Figure 19. HC Low-Speed Threshold Register (HCLSTHRESHOLD)
31
16
Reserved
R-0
15
14
13
0
Reserved
LST
R-0
R/W-628h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. HC Low-Speed Threshold Register (HCLSTHRESHOLD) Field Descriptions
Bit
Field
Value
Description
31-14
Reserved
0
Reserved
13-0
LST
0-3FFFh
Low-speed threshold. This field defines the number of full-speed bit times in the frame after which
the USB host controller cannot start an 8-byte low-speed packet. The USB host controller only
begins a low-speed transaction if the frame remaining (FR) value in the HC frame remaining
register (HCFMREMAINING) is greater than the low-speed threshold.
the USB host controller cannot start an 8-byte low-speed packet. The USB host controller only
begins a low-speed transaction if the frame remaining (FR) value in the HC frame remaining
register (HCFMREMAINING) is greater than the low-speed threshold.
The host controller driver must set this field to a value that ensures that an 8-byte low-speed TD
completes before the end of the frame. When set, the host controller driver must not change the
value.
completes before the end of the frame. When set, the host controller driver must not change the
value.
Universal Serial Bus OHCI Host Controller
26
SPRUFM8 – September 2008