Intel 253668-032US Benutzerhandbuch
13-12 Vol. 3
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR
If a new task attempts to access an x87 FPU, MMX, XMM, or MXCSR register while the
TS flag is set to 1, a device-not-available exception (#NM) is generated. The device-
not-available exception handler executes the following pseudo-code.
TS flag is set to 1, a device-not-available exception (#NM) is generated. The device-
not-available exception handler executes the following pseudo-code.
FXSAVE “To x87FPU/MMX/XMM/MXCSR State Save Area for Current
x87FPU_MMX_XMM_MXCSR_StateOwner”;
FXRSTOR “x87FPU/MMX/XMM/MXCSR State From Current Task’s
x87FPU/MMX/XMM/MXCSR State Save Area”;
x87FPU_MMX_XMM_MXCSR_StateOwner ← Current_Task;
CR0.TS ← 0;
This exception handler code performs the following tasks:
CR0.TS ← 0;
This exception handler code performs the following tasks:
•
Saves the x87 FPU, MMX, XMM, or MXCSR registers in the state save area for the
current owner of the x87 FPU/MMX/XMM/MXCSR state.
current owner of the x87 FPU/MMX/XMM/MXCSR state.
•
Restores the x87 FPU, MMX, XMM, or MXCSR registers from the new task’s save
area for the x87 FPU/MMX/XMM/MXCSR state.
area for the x87 FPU/MMX/XMM/MXCSR state.
•
Updates the current x87 FPU/MMX/XMM/MXCSR state owner to be the current
task.
task.
•
Clears the TS flag.
13.6
XSAVE/XRSTOR AND PROCESSOR EXTENDED STATE
MANAGEMENT
The features associated with managing processor extended states include
•
An extensible data layout for existing and future processor state extensions. The
layout of the XSAVE/XRSTOR area extends from the 512-byte FXSAVE/FXRSTOR
layout to provide compatibility and migration path from managing the legacy
FXSAVE/FXRSTOR area. Specifically, the XSAVE/XRSTOR area layout consists of:
— The FXSAVE/FXRSTOR area (512 bytes, the layout is identical to the
layout of the XSAVE/XRSTOR area extends from the 512-byte FXSAVE/FXRSTOR
layout to provide compatibility and migration path from managing the legacy
FXSAVE/FXRSTOR area. Specifically, the XSAVE/XRSTOR area layout consists of:
— The FXSAVE/FXRSTOR area (512 bytes, the layout is identical to the
FXSAVE/FXRSTOR area),
— The XSAVE header area (64 bytes),
— A finite set of save areas, each corresponding to a processor extended state
— A finite set of save areas, each corresponding to a processor extended state
(see Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2B, XSAVE instruction). The number of save areas, the offset and the
size of each save area is enumerated by CPUID leaf function 0DH.
Volume 2B, XSAVE instruction). The number of save areas, the offset and the
size of each save area is enumerated by CPUID leaf function 0DH.
•
CPUID Enhancement: CPUID instruction provides information on
— CPUID.01H.ECX.XSAVE[bit 26]. A feature flag indicating the processor’s
— CPUID.01H.ECX.XSAVE[bit 26]. A feature flag indicating the processor’s
support of XSAVE/XRSTOR architecture extensions
— CPUID.01H.ECX.OSXSAVE[bit 27]. A feature flag indicating whether OS has
enabled extensible state management and communicating that the OS
supports processor extended state management.
supports processor extended state management.