Intel 253668-032US Benutzerhandbuch
Vol. 3 13-13
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND
— CPUID leaf function 0DH enumerates the list of processor states (including
legacy x87 FPU, SSE states and processor extended states), the offset and
size of individual save area for each processor extended state.
size of individual save area for each processor extended state.
•
Control register enhancement and dedicated register for enabling each processor
extended state: CR4. OSXSAVE[bit 18] and the XFEATURE_ENABLED_MASK
register (XCR0) are described in Chapter 2, “System Architecture Overview”.
XCR0 can be read at all privilege levels but written only at ring 0.
extended state: CR4. OSXSAVE[bit 18] and the XFEATURE_ENABLED_MASK
register (XCR0) are described in Chapter 2, “System Architecture Overview”.
XCR0 can be read at all privilege levels but written only at ring 0.
•
Instructions to manage the XFEATURE_ENABLED_MASK register (XCR0) and the
XSAVE/XRSTOR area (see Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2B):
— XGETBV: reads XCR0.
— XSETBV: writes to XCR0, ring 0 only.
— XRSTOR: restores from memory the processor states specified by a bit vector
XSAVE/XRSTOR area (see Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2B):
— XGETBV: reads XCR0.
— XSETBV: writes to XCR0, ring 0 only.
— XRSTOR: restores from memory the processor states specified by a bit vector
mask specified in EDX:EAX.
— XSAVE: saves the current processor states to memory according to a bit
vector mask in EDX:EAX.
13.6.1 XSAVE
Header
The header section includes a “XSTATE_BV“ bit vector field. If the value of a bit in
HEADER.XSTATE_BV is 1, it indicates that the corresponding processor extended
state was written to the respective save area in memory by the XSAVE instruction.
If software modifies the save area image of a particular processor state component
directly, it is responsible to update the corresponding bit in HEADER.XSTATE_BV to 1.
Otherwise, directly modified state information in a save area image may be ignored
by XRSTOR.
The order of bit vectors in XSTATE_BV matches those of the
XFEATURE_ENABLED_MASK register (XCR0). Although XCR0 has only two bits
initially defined for state management, the general relationship between the value of
XSTATE_BV and the corresponding processor state in the XSAVE/XRSTOR layout is
depicted in Figure 13-2.
HEADER.XSTATE_BV is 1, it indicates that the corresponding processor extended
state was written to the respective save area in memory by the XSAVE instruction.
If software modifies the save area image of a particular processor state component
directly, it is responsible to update the corresponding bit in HEADER.XSTATE_BV to 1.
Otherwise, directly modified state information in a save area image may be ignored
by XRSTOR.
The order of bit vectors in XSTATE_BV matches those of the
XFEATURE_ENABLED_MASK register (XCR0). Although XCR0 has only two bits
initially defined for state management, the general relationship between the value of
XSTATE_BV and the corresponding processor state in the XSAVE/XRSTOR layout is
depicted in Figure 13-2.