Intel 253668-032US Benutzerhandbuch
13-14 Vol. 3
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR
The XSAVE header is 64 bytes in length and must be aligned on 64 byte boundary.
Therefore, the XSAVE/XRSTOR region must be aligned on 64-byte boundary. The
format of the header is as follows (see Table 13-3):
Therefore, the XSAVE/XRSTOR region must be aligned on 64-byte boundary. The
format of the header is as follows (see Table 13-3):
The value of each bit in HEADER.XSTATE_BV may affect the action performed by
XRSTOR, depending on the logical value of the respective bits in the
XFEATURE_ENABLED_MASK register (XCR0), the restore bit mask (EDX:EAX input to
XRSTOR), and HEADER.XSTATE_BV. When an XRSTOR instruction is executed with a
restore bit mask selecting the i’th bit vector (and the corresponding XCR0 bit is
XRSTOR, depending on the logical value of the respective bits in the
XFEATURE_ENABLED_MASK register (XCR0), the restore bit mask (EDX:EAX input to
XRSTOR), and HEADER.XSTATE_BV. When an XRSTOR instruction is executed with a
restore bit mask selecting the i’th bit vector (and the corresponding XCR0 bit is
Figure 13-2. Future Layout of XSAVE/XRSTOR Area and XSTATE_BV with Five Sets
of Processor State Extensions
Table 13-3. XSAVE Header Format
15:8
7:0
Byte Offset
Reserved (Must be zero)
XSTATE_BV
0
Reserved
Reserved (Must be zero)
16
Reserved
Reserved
32
Reserved
Reserved
48
..................................
XState_BV
Extensions 2
X87 FPU State
Save Area
0
1
2
4
3
FXSAVE
63
SSE State
FXRSTOR
XState_BV, ..
Header
Ext_SaveArea2
.........................
Exten
s
ions 4
Ext_SaveArea3
1
1
1
1
0
Bit Position
Extensions 3
Updated
Not updated
Updated
Ext_SaveArea4