Intel 253668-032US Benutzerhandbuch
Vol. 3 13-15
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND
enabled), a value of "1" in the corresponding bit of HEADER.XSTATE_BV causes the
processor state to be updated with contents of the save area read from the memory
image. A value of "0" in HEADER.XSTATE_BV causes the processor state to be initial-
ized by hardware supplied values instead of from memory (See the operation detail
of XRSTOR in Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2B).
The save area image corresponding to a bit with "0" value in HEADER.XSTATE_BV
may or may not contain the correct state information. XRSTOR will ensure the
register state for a component is properly initialized regardless of the value of the
save area when the component header bit is zero.
processor state to be updated with contents of the save area read from the memory
image. A value of "0" in HEADER.XSTATE_BV causes the processor state to be initial-
ized by hardware supplied values instead of from memory (See the operation detail
of XRSTOR in Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2B).
The save area image corresponding to a bit with "0" value in HEADER.XSTATE_BV
may or may not contain the correct state information. XRSTOR will ensure the
register state for a component is properly initialized regardless of the value of the
save area when the component header bit is zero.
13.7
INTEROPERABILITY OF XSAVE/XRSTOR AND
FXSAVE/FXRSTOR
FXSAVE instruction writes x87 FPU and SSE state information to a 512-byte FXSAVE,
FXRSTOR save area. FXRSTOR restores the processor’s x87 FPU and SSE states from
FXSAVE/FXRSTOR save area image. XSAVE/XRSTOR instructions support x87 FPU
and SSE states using the same layout as the FXSAVE/FXRSTOR area to provide
interoperability of FXSAVE versus XSAVE, and FXRSTOR versus XRSTOR.
XSAVE/XRSTOR provides the additional flexibility for system software to manage SSE
state independent of x87 FPU states. Thus system software that had been using
FXSAVE/FXRSTOR to manage x87 FPU and SSE states can transition to
XSAVE/XRSTOR to manage x87 FPU, SSE and other processor extended states in a
systematic and forward-looking manner.
It is also possible for system software to adopt an alternate approach of using
FXSAVE/FXRSTOR for x87 and SSE state management, and implementing forward
processor extended state management using XSAVE/XRSTOR. In this case, system
software must specify the bit vector mask in EDX:EAX appropriately when executing
XSAVE/XRSTOR instructions.
For instance, when using the XSAVE instruction, the OS can supply a bit vector in
EDX:EAX with the two least significant bits corresponding to x87 FPU and SSE state
equal to 0. Then, the XSAVE instruction will not write the processor’s x87 FPU and
SSE state into memory. Similarly for the XRSTOR instruction a bit vector mask in
EDX:EAX with the least two significant bit equal to 0 will cause the XRSTOR instruc-
tion to not restore nor initialize the processor’s x87 FPU and SSE state.
The processor’s action as a result of executing XRSTOR, on the x87 FPU state,
MXCSR, and XMM registers, are listed in Table 13-4 (Both bit 1 and bit 0 of the
XFEATURE_ENABLED_MASK register are presumed to be 1). The x87 FPU or XMM
registers may be initialized by the processor (See XRSTOR operation in Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 2B). When the MXCSR
register is updated from memory, reserved bit checking is enforced. The
saving/restoring of MXCSR is bound to the SSE state, independent of the x87 FPU
state. The action of XSAVE is listed in Table 13-5.
FXRSTOR save area. FXRSTOR restores the processor’s x87 FPU and SSE states from
FXSAVE/FXRSTOR save area image. XSAVE/XRSTOR instructions support x87 FPU
and SSE states using the same layout as the FXSAVE/FXRSTOR area to provide
interoperability of FXSAVE versus XSAVE, and FXRSTOR versus XRSTOR.
XSAVE/XRSTOR provides the additional flexibility for system software to manage SSE
state independent of x87 FPU states. Thus system software that had been using
FXSAVE/FXRSTOR to manage x87 FPU and SSE states can transition to
XSAVE/XRSTOR to manage x87 FPU, SSE and other processor extended states in a
systematic and forward-looking manner.
It is also possible for system software to adopt an alternate approach of using
FXSAVE/FXRSTOR for x87 and SSE state management, and implementing forward
processor extended state management using XSAVE/XRSTOR. In this case, system
software must specify the bit vector mask in EDX:EAX appropriately when executing
XSAVE/XRSTOR instructions.
For instance, when using the XSAVE instruction, the OS can supply a bit vector in
EDX:EAX with the two least significant bits corresponding to x87 FPU and SSE state
equal to 0. Then, the XSAVE instruction will not write the processor’s x87 FPU and
SSE state into memory. Similarly for the XRSTOR instruction a bit vector mask in
EDX:EAX with the least two significant bit equal to 0 will cause the XRSTOR instruc-
tion to not restore nor initialize the processor’s x87 FPU and SSE state.
The processor’s action as a result of executing XRSTOR, on the x87 FPU state,
MXCSR, and XMM registers, are listed in Table 13-4 (Both bit 1 and bit 0 of the
XFEATURE_ENABLED_MASK register are presumed to be 1). The x87 FPU or XMM
registers may be initialized by the processor (See XRSTOR operation in Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 2B). When the MXCSR
register is updated from memory, reserved bit checking is enforced. The
saving/restoring of MXCSR is bound to the SSE state, independent of the x87 FPU
state. The action of XSAVE is listed in Table 13-5.